1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ALPHAPROJECT AP-SH4A-3A Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd.
6*4882a593Smuzhiyun * Copyright (C) 2008 Yoshihiro Shimoda
7*4882a593Smuzhiyun * Copyright (C) 2009 Paul Mundt
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
13*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
14*4882a593Smuzhiyun #include <linux/regulator/machine.h>
15*4882a593Smuzhiyun #include <linux/smsc911x.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <linux/clk.h>
18*4882a593Smuzhiyun #include <asm/machvec.h>
19*4882a593Smuzhiyun #include <linux/sizes.h>
20*4882a593Smuzhiyun #include <asm/clock.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static struct mtd_partition nor_flash_partitions[] = {
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun .name = "loader",
25*4882a593Smuzhiyun .offset = 0x00000000,
26*4882a593Smuzhiyun .size = 512 * 1024,
27*4882a593Smuzhiyun },
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun .name = "bootenv",
30*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
31*4882a593Smuzhiyun .size = 512 * 1024,
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun .name = "kernel",
35*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
36*4882a593Smuzhiyun .size = 4 * 1024 * 1024,
37*4882a593Smuzhiyun },
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun .name = "data",
40*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
41*4882a593Smuzhiyun .size = MTDPART_SIZ_FULL,
42*4882a593Smuzhiyun },
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static struct physmap_flash_data nor_flash_data = {
46*4882a593Smuzhiyun .width = 4,
47*4882a593Smuzhiyun .parts = nor_flash_partitions,
48*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(nor_flash_partitions),
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static struct resource nor_flash_resources[] = {
52*4882a593Smuzhiyun [0] = {
53*4882a593Smuzhiyun .start = 0x00000000,
54*4882a593Smuzhiyun .end = 0x01000000 - 1,
55*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static struct platform_device nor_flash_device = {
60*4882a593Smuzhiyun .name = "physmap-flash",
61*4882a593Smuzhiyun .dev = {
62*4882a593Smuzhiyun .platform_data = &nor_flash_data,
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(nor_flash_resources),
65*4882a593Smuzhiyun .resource = nor_flash_resources,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Dummy supplies, where voltage doesn't matter */
69*4882a593Smuzhiyun static struct regulator_consumer_supply dummy_supplies[] = {
70*4882a593Smuzhiyun REGULATOR_SUPPLY("vddvario", "smsc911x"),
71*4882a593Smuzhiyun REGULATOR_SUPPLY("vdd33a", "smsc911x"),
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static struct resource smsc911x_resources[] = {
75*4882a593Smuzhiyun [0] = {
76*4882a593Smuzhiyun .name = "smsc911x-memory",
77*4882a593Smuzhiyun .start = 0xA4000000,
78*4882a593Smuzhiyun .end = 0xA4000000 + SZ_256 - 1,
79*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
80*4882a593Smuzhiyun },
81*4882a593Smuzhiyun [1] = {
82*4882a593Smuzhiyun .name = "smsc911x-irq",
83*4882a593Smuzhiyun .start = evt2irq(0x200),
84*4882a593Smuzhiyun .end = evt2irq(0x200),
85*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
86*4882a593Smuzhiyun },
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static struct smsc911x_platform_config smsc911x_config = {
90*4882a593Smuzhiyun .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
91*4882a593Smuzhiyun .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
92*4882a593Smuzhiyun .flags = SMSC911X_USE_16BIT,
93*4882a593Smuzhiyun .phy_interface = PHY_INTERFACE_MODE_MII,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static struct platform_device smsc911x_device = {
97*4882a593Smuzhiyun .name = "smsc911x",
98*4882a593Smuzhiyun .id = -1,
99*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(smsc911x_resources),
100*4882a593Smuzhiyun .resource = smsc911x_resources,
101*4882a593Smuzhiyun .dev = {
102*4882a593Smuzhiyun .platform_data = &smsc911x_config,
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static struct platform_device *apsh4a3a_devices[] __initdata = {
107*4882a593Smuzhiyun &nor_flash_device,
108*4882a593Smuzhiyun &smsc911x_device,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
apsh4a3a_devices_setup(void)111*4882a593Smuzhiyun static int __init apsh4a3a_devices_setup(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return platform_add_devices(apsh4a3a_devices,
116*4882a593Smuzhiyun ARRAY_SIZE(apsh4a3a_devices));
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun device_initcall(apsh4a3a_devices_setup);
119*4882a593Smuzhiyun
apsh4a3a_clk_init(void)120*4882a593Smuzhiyun static int apsh4a3a_clk_init(void)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct clk *clk;
123*4882a593Smuzhiyun int ret;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun clk = clk_get(NULL, "extal");
126*4882a593Smuzhiyun if (IS_ERR(clk))
127*4882a593Smuzhiyun return PTR_ERR(clk);
128*4882a593Smuzhiyun ret = clk_set_rate(clk, 33333000);
129*4882a593Smuzhiyun clk_put(clk);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return ret;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* Initialize the board */
apsh4a3a_setup(char ** cmdline_p)135*4882a593Smuzhiyun static void __init apsh4a3a_setup(char **cmdline_p)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun printk(KERN_INFO "Alpha Project AP-SH4A-3A support:\n");
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
apsh4a3a_init_irq(void)140*4882a593Smuzhiyun static void __init apsh4a3a_init_irq(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun plat_irq_setup_pins(IRQ_MODE_IRQ7654);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* Return the board specific boot mode pin configuration */
apsh4a3a_mode_pins(void)146*4882a593Smuzhiyun static int apsh4a3a_mode_pins(void)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun int value = 0;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* These are the factory default settings of SW1 and SW2.
151*4882a593Smuzhiyun * If you change these dip switches then you will need to
152*4882a593Smuzhiyun * adjust the values below as well.
153*4882a593Smuzhiyun */
154*4882a593Smuzhiyun value &= ~MODE_PIN0; /* Clock Mode 16 */
155*4882a593Smuzhiyun value &= ~MODE_PIN1;
156*4882a593Smuzhiyun value &= ~MODE_PIN2;
157*4882a593Smuzhiyun value &= ~MODE_PIN3;
158*4882a593Smuzhiyun value |= MODE_PIN4;
159*4882a593Smuzhiyun value &= ~MODE_PIN5; /* 16-bit Area0 bus width */
160*4882a593Smuzhiyun value |= MODE_PIN6; /* Area 0 SRAM interface */
161*4882a593Smuzhiyun value |= MODE_PIN7;
162*4882a593Smuzhiyun value |= MODE_PIN8; /* Little Endian */
163*4882a593Smuzhiyun value |= MODE_PIN9; /* Master Mode */
164*4882a593Smuzhiyun value |= MODE_PIN10; /* Crystal resonator */
165*4882a593Smuzhiyun value |= MODE_PIN11; /* Display Unit */
166*4882a593Smuzhiyun value |= MODE_PIN12;
167*4882a593Smuzhiyun value &= ~MODE_PIN13; /* 29-bit address mode */
168*4882a593Smuzhiyun value |= MODE_PIN14; /* No PLL step-up */
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return value;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /*
174*4882a593Smuzhiyun * The Machine Vector
175*4882a593Smuzhiyun */
176*4882a593Smuzhiyun static struct sh_machine_vector mv_apsh4a3a __initmv = {
177*4882a593Smuzhiyun .mv_name = "AP-SH4A-3A",
178*4882a593Smuzhiyun .mv_setup = apsh4a3a_setup,
179*4882a593Smuzhiyun .mv_clk_init = apsh4a3a_clk_init,
180*4882a593Smuzhiyun .mv_init_irq = apsh4a3a_init_irq,
181*4882a593Smuzhiyun .mv_mode_pins = apsh4a3a_mode_pins,
182*4882a593Smuzhiyun };
183