1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * S390 version
4*4882a593Smuzhiyun * Copyright IBM Corp. 1999, 2000
5*4882a593Smuzhiyun * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef _S390_PTRACE_H
8*4882a593Smuzhiyun #define _S390_PTRACE_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/bits.h>
11*4882a593Smuzhiyun #include <uapi/asm/ptrace.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define PIF_SYSCALL 0 /* inside a system call */
14*4882a593Smuzhiyun #define PIF_PER_TRAP 1 /* deliver sigtrap on return to user */
15*4882a593Smuzhiyun #define PIF_SYSCALL_RESTART 2 /* restart the current system call */
16*4882a593Smuzhiyun #define PIF_GUEST_FAULT 3 /* indicates program check in sie64a */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define _PIF_SYSCALL BIT(PIF_SYSCALL)
19*4882a593Smuzhiyun #define _PIF_PER_TRAP BIT(PIF_PER_TRAP)
20*4882a593Smuzhiyun #define _PIF_SYSCALL_RESTART BIT(PIF_SYSCALL_RESTART)
21*4882a593Smuzhiyun #define _PIF_GUEST_FAULT BIT(PIF_GUEST_FAULT)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #ifndef __ASSEMBLY__
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define PSW_KERNEL_BITS (PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_ASC_HOME | \
26*4882a593Smuzhiyun PSW_MASK_EA | PSW_MASK_BA)
27*4882a593Smuzhiyun #define PSW_USER_BITS (PSW_MASK_DAT | PSW_MASK_IO | PSW_MASK_EXT | \
28*4882a593Smuzhiyun PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_MCHECK | \
29*4882a593Smuzhiyun PSW_MASK_PSTATE | PSW_ASC_PRIMARY)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct psw_bits {
32*4882a593Smuzhiyun unsigned long : 1;
33*4882a593Smuzhiyun unsigned long per : 1; /* PER-Mask */
34*4882a593Smuzhiyun unsigned long : 3;
35*4882a593Smuzhiyun unsigned long dat : 1; /* DAT Mode */
36*4882a593Smuzhiyun unsigned long io : 1; /* Input/Output Mask */
37*4882a593Smuzhiyun unsigned long ext : 1; /* External Mask */
38*4882a593Smuzhiyun unsigned long key : 4; /* PSW Key */
39*4882a593Smuzhiyun unsigned long : 1;
40*4882a593Smuzhiyun unsigned long mcheck : 1; /* Machine-Check Mask */
41*4882a593Smuzhiyun unsigned long wait : 1; /* Wait State */
42*4882a593Smuzhiyun unsigned long pstate : 1; /* Problem State */
43*4882a593Smuzhiyun unsigned long as : 2; /* Address Space Control */
44*4882a593Smuzhiyun unsigned long cc : 2; /* Condition Code */
45*4882a593Smuzhiyun unsigned long pm : 4; /* Program Mask */
46*4882a593Smuzhiyun unsigned long ri : 1; /* Runtime Instrumentation */
47*4882a593Smuzhiyun unsigned long : 6;
48*4882a593Smuzhiyun unsigned long eaba : 2; /* Addressing Mode */
49*4882a593Smuzhiyun unsigned long : 31;
50*4882a593Smuzhiyun unsigned long ia : 64; /* Instruction Address */
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun enum {
54*4882a593Smuzhiyun PSW_BITS_AMODE_24BIT = 0,
55*4882a593Smuzhiyun PSW_BITS_AMODE_31BIT = 1,
56*4882a593Smuzhiyun PSW_BITS_AMODE_64BIT = 3
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun enum {
60*4882a593Smuzhiyun PSW_BITS_AS_PRIMARY = 0,
61*4882a593Smuzhiyun PSW_BITS_AS_ACCREG = 1,
62*4882a593Smuzhiyun PSW_BITS_AS_SECONDARY = 2,
63*4882a593Smuzhiyun PSW_BITS_AS_HOME = 3
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define psw_bits(__psw) (*({ \
67*4882a593Smuzhiyun typecheck(psw_t, __psw); \
68*4882a593Smuzhiyun &(*(struct psw_bits *)(&(__psw))); \
69*4882a593Smuzhiyun }))
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * The pt_regs struct defines the way the registers are stored on
73*4882a593Smuzhiyun * the stack during a system call.
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun struct pt_regs
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun union {
78*4882a593Smuzhiyun user_pt_regs user_regs;
79*4882a593Smuzhiyun struct {
80*4882a593Smuzhiyun unsigned long args[1];
81*4882a593Smuzhiyun psw_t psw;
82*4882a593Smuzhiyun unsigned long gprs[NUM_GPRS];
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun unsigned long orig_gpr2;
86*4882a593Smuzhiyun unsigned int int_code;
87*4882a593Smuzhiyun unsigned int int_parm;
88*4882a593Smuzhiyun unsigned long int_parm_long;
89*4882a593Smuzhiyun unsigned long flags;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * Program event recording (PER) register set.
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun struct per_regs {
96*4882a593Smuzhiyun unsigned long control; /* PER control bits */
97*4882a593Smuzhiyun unsigned long start; /* PER starting address */
98*4882a593Smuzhiyun unsigned long end; /* PER ending address */
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun * PER event contains information about the cause of the last PER exception.
103*4882a593Smuzhiyun */
104*4882a593Smuzhiyun struct per_event {
105*4882a593Smuzhiyun unsigned short cause; /* PER code, ATMID and AI */
106*4882a593Smuzhiyun unsigned long address; /* PER address */
107*4882a593Smuzhiyun unsigned char paid; /* PER access identification */
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun * Simplified per_info structure used to decode the ptrace user space ABI.
112*4882a593Smuzhiyun */
113*4882a593Smuzhiyun struct per_struct_kernel {
114*4882a593Smuzhiyun unsigned long cr9; /* PER control bits */
115*4882a593Smuzhiyun unsigned long cr10; /* PER starting address */
116*4882a593Smuzhiyun unsigned long cr11; /* PER ending address */
117*4882a593Smuzhiyun unsigned long bits; /* Obsolete software bits */
118*4882a593Smuzhiyun unsigned long starting_addr; /* User specified start address */
119*4882a593Smuzhiyun unsigned long ending_addr; /* User specified end address */
120*4882a593Smuzhiyun unsigned short perc_atmid; /* PER trap ATMID */
121*4882a593Smuzhiyun unsigned long address; /* PER trap instruction address */
122*4882a593Smuzhiyun unsigned char access_id; /* PER trap access identification */
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #define PER_EVENT_MASK 0xEB000000UL
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #define PER_EVENT_BRANCH 0x80000000UL
128*4882a593Smuzhiyun #define PER_EVENT_IFETCH 0x40000000UL
129*4882a593Smuzhiyun #define PER_EVENT_STORE 0x20000000UL
130*4882a593Smuzhiyun #define PER_EVENT_STORE_REAL 0x08000000UL
131*4882a593Smuzhiyun #define PER_EVENT_TRANSACTION_END 0x02000000UL
132*4882a593Smuzhiyun #define PER_EVENT_NULLIFICATION 0x01000000UL
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #define PER_CONTROL_MASK 0x00e00000UL
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define PER_CONTROL_BRANCH_ADDRESS 0x00800000UL
137*4882a593Smuzhiyun #define PER_CONTROL_SUSPENSION 0x00400000UL
138*4882a593Smuzhiyun #define PER_CONTROL_ALTERATION 0x00200000UL
139*4882a593Smuzhiyun
set_pt_regs_flag(struct pt_regs * regs,int flag)140*4882a593Smuzhiyun static inline void set_pt_regs_flag(struct pt_regs *regs, int flag)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun regs->flags |= (1UL << flag);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
clear_pt_regs_flag(struct pt_regs * regs,int flag)145*4882a593Smuzhiyun static inline void clear_pt_regs_flag(struct pt_regs *regs, int flag)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun regs->flags &= ~(1UL << flag);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
test_pt_regs_flag(struct pt_regs * regs,int flag)150*4882a593Smuzhiyun static inline int test_pt_regs_flag(struct pt_regs *regs, int flag)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun return !!(regs->flags & (1UL << flag));
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /*
156*4882a593Smuzhiyun * These are defined as per linux/ptrace.h, which see.
157*4882a593Smuzhiyun */
158*4882a593Smuzhiyun #define arch_has_single_step() (1)
159*4882a593Smuzhiyun #define arch_has_block_step() (1)
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
162*4882a593Smuzhiyun #define instruction_pointer(regs) ((regs)->psw.addr)
163*4882a593Smuzhiyun #define user_stack_pointer(regs)((regs)->gprs[15])
164*4882a593Smuzhiyun #define profile_pc(regs) instruction_pointer(regs)
165*4882a593Smuzhiyun
regs_return_value(struct pt_regs * regs)166*4882a593Smuzhiyun static inline long regs_return_value(struct pt_regs *regs)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun return regs->gprs[2];
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
instruction_pointer_set(struct pt_regs * regs,unsigned long val)171*4882a593Smuzhiyun static inline void instruction_pointer_set(struct pt_regs *regs,
172*4882a593Smuzhiyun unsigned long val)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun regs->psw.addr = val;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun int regs_query_register_offset(const char *name);
178*4882a593Smuzhiyun const char *regs_query_register_name(unsigned int offset);
179*4882a593Smuzhiyun unsigned long regs_get_register(struct pt_regs *regs, unsigned int offset);
180*4882a593Smuzhiyun unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n);
181*4882a593Smuzhiyun
kernel_stack_pointer(struct pt_regs * regs)182*4882a593Smuzhiyun static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun return regs->gprs[15];
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
regs_set_return_value(struct pt_regs * regs,unsigned long rc)187*4882a593Smuzhiyun static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun regs->gprs[2] = rc;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */
193*4882a593Smuzhiyun #endif /* _S390_PTRACE_H */
194