1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _ASM_S390_PCI_INSN_H
3*4882a593Smuzhiyun #define _ASM_S390_PCI_INSN_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/jump_label.h>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /* Load/Store status codes */
8*4882a593Smuzhiyun #define ZPCI_PCI_ST_FUNC_NOT_ENABLED 4
9*4882a593Smuzhiyun #define ZPCI_PCI_ST_FUNC_IN_ERR 8
10*4882a593Smuzhiyun #define ZPCI_PCI_ST_BLOCKED 12
11*4882a593Smuzhiyun #define ZPCI_PCI_ST_INSUF_RES 16
12*4882a593Smuzhiyun #define ZPCI_PCI_ST_INVAL_AS 20
13*4882a593Smuzhiyun #define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED 24
14*4882a593Smuzhiyun #define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED 28
15*4882a593Smuzhiyun #define ZPCI_PCI_ST_2ND_OP_IN_INV_AS 36
16*4882a593Smuzhiyun #define ZPCI_PCI_ST_FUNC_NOT_AVAIL 40
17*4882a593Smuzhiyun #define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE 44
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Load/Store return codes */
20*4882a593Smuzhiyun #define ZPCI_PCI_LS_OK 0
21*4882a593Smuzhiyun #define ZPCI_PCI_LS_ERR 1
22*4882a593Smuzhiyun #define ZPCI_PCI_LS_BUSY 2
23*4882a593Smuzhiyun #define ZPCI_PCI_LS_INVAL_HANDLE 3
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Load/Store address space identifiers */
26*4882a593Smuzhiyun #define ZPCI_PCIAS_MEMIO_0 0
27*4882a593Smuzhiyun #define ZPCI_PCIAS_MEMIO_1 1
28*4882a593Smuzhiyun #define ZPCI_PCIAS_MEMIO_2 2
29*4882a593Smuzhiyun #define ZPCI_PCIAS_MEMIO_3 3
30*4882a593Smuzhiyun #define ZPCI_PCIAS_MEMIO_4 4
31*4882a593Smuzhiyun #define ZPCI_PCIAS_MEMIO_5 5
32*4882a593Smuzhiyun #define ZPCI_PCIAS_CFGSPC 15
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Modify PCI Function Controls */
35*4882a593Smuzhiyun #define ZPCI_MOD_FC_REG_INT 2
36*4882a593Smuzhiyun #define ZPCI_MOD_FC_DEREG_INT 3
37*4882a593Smuzhiyun #define ZPCI_MOD_FC_REG_IOAT 4
38*4882a593Smuzhiyun #define ZPCI_MOD_FC_DEREG_IOAT 5
39*4882a593Smuzhiyun #define ZPCI_MOD_FC_REREG_IOAT 6
40*4882a593Smuzhiyun #define ZPCI_MOD_FC_RESET_ERROR 7
41*4882a593Smuzhiyun #define ZPCI_MOD_FC_RESET_BLOCK 9
42*4882a593Smuzhiyun #define ZPCI_MOD_FC_SET_MEASURE 10
43*4882a593Smuzhiyun #define ZPCI_MOD_FC_REG_INT_D 16
44*4882a593Smuzhiyun #define ZPCI_MOD_FC_DEREG_INT_D 17
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* FIB function controls */
47*4882a593Smuzhiyun #define ZPCI_FIB_FC_ENABLED 0x80
48*4882a593Smuzhiyun #define ZPCI_FIB_FC_ERROR 0x40
49*4882a593Smuzhiyun #define ZPCI_FIB_FC_LS_BLOCKED 0x20
50*4882a593Smuzhiyun #define ZPCI_FIB_FC_DMAAS_REG 0x10
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* FIB function controls */
53*4882a593Smuzhiyun #define ZPCI_FIB_FC_ENABLED 0x80
54*4882a593Smuzhiyun #define ZPCI_FIB_FC_ERROR 0x40
55*4882a593Smuzhiyun #define ZPCI_FIB_FC_LS_BLOCKED 0x20
56*4882a593Smuzhiyun #define ZPCI_FIB_FC_DMAAS_REG 0x10
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun struct zpci_fib_fmt0 {
59*4882a593Smuzhiyun u32 : 1;
60*4882a593Smuzhiyun u32 isc : 3; /* Interrupt subclass */
61*4882a593Smuzhiyun u32 noi : 12; /* Number of interrupts */
62*4882a593Smuzhiyun u32 : 2;
63*4882a593Smuzhiyun u32 aibvo : 6; /* Adapter interrupt bit vector offset */
64*4882a593Smuzhiyun u32 sum : 1; /* Adapter int summary bit enabled */
65*4882a593Smuzhiyun u32 : 1;
66*4882a593Smuzhiyun u32 aisbo : 6; /* Adapter int summary bit offset */
67*4882a593Smuzhiyun u32 : 32;
68*4882a593Smuzhiyun u64 aibv; /* Adapter int bit vector address */
69*4882a593Smuzhiyun u64 aisb; /* Adapter int summary bit address */
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct zpci_fib_fmt1 {
73*4882a593Smuzhiyun u32 : 4;
74*4882a593Smuzhiyun u32 noi : 12;
75*4882a593Smuzhiyun u32 : 16;
76*4882a593Smuzhiyun u32 dibvo : 16;
77*4882a593Smuzhiyun u32 : 16;
78*4882a593Smuzhiyun u64 : 64;
79*4882a593Smuzhiyun u64 : 64;
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Function Information Block */
83*4882a593Smuzhiyun struct zpci_fib {
84*4882a593Smuzhiyun u32 fmt : 8; /* format */
85*4882a593Smuzhiyun u32 : 24;
86*4882a593Smuzhiyun u32 : 32;
87*4882a593Smuzhiyun u8 fc; /* function controls */
88*4882a593Smuzhiyun u64 : 56;
89*4882a593Smuzhiyun u64 pba; /* PCI base address */
90*4882a593Smuzhiyun u64 pal; /* PCI address limit */
91*4882a593Smuzhiyun u64 iota; /* I/O Translation Anchor */
92*4882a593Smuzhiyun union {
93*4882a593Smuzhiyun struct zpci_fib_fmt0 fmt0;
94*4882a593Smuzhiyun struct zpci_fib_fmt1 fmt1;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun u64 fmb_addr; /* Function measurement block address and key */
97*4882a593Smuzhiyun u32 : 32;
98*4882a593Smuzhiyun u32 gd;
99*4882a593Smuzhiyun } __packed __aligned(8);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* directed interruption information block */
102*4882a593Smuzhiyun struct zpci_diib {
103*4882a593Smuzhiyun u32 : 1;
104*4882a593Smuzhiyun u32 isc : 3;
105*4882a593Smuzhiyun u32 : 28;
106*4882a593Smuzhiyun u16 : 16;
107*4882a593Smuzhiyun u16 nr_cpus;
108*4882a593Smuzhiyun u64 disb_addr;
109*4882a593Smuzhiyun u64 : 64;
110*4882a593Smuzhiyun u64 : 64;
111*4882a593Smuzhiyun } __packed __aligned(8);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* cpu directed interruption information block */
114*4882a593Smuzhiyun struct zpci_cdiib {
115*4882a593Smuzhiyun u64 : 64;
116*4882a593Smuzhiyun u64 dibv_addr;
117*4882a593Smuzhiyun u64 : 64;
118*4882a593Smuzhiyun u64 : 64;
119*4882a593Smuzhiyun u64 : 64;
120*4882a593Smuzhiyun } __packed __aligned(8);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun union zpci_sic_iib {
123*4882a593Smuzhiyun struct zpci_diib diib;
124*4882a593Smuzhiyun struct zpci_cdiib cdiib;
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun DECLARE_STATIC_KEY_FALSE(have_mio);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status);
130*4882a593Smuzhiyun int zpci_refresh_trans(u64 fn, u64 addr, u64 range);
131*4882a593Smuzhiyun int __zpci_load(u64 *data, u64 req, u64 offset);
132*4882a593Smuzhiyun int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len);
133*4882a593Smuzhiyun int __zpci_store(u64 data, u64 req, u64 offset);
134*4882a593Smuzhiyun int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len);
135*4882a593Smuzhiyun int __zpci_store_block(const u64 *data, u64 req, u64 offset);
136*4882a593Smuzhiyun void zpci_barrier(void);
137*4882a593Smuzhiyun int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib);
138*4882a593Smuzhiyun
zpci_set_irq_ctrl(u16 ctl,u8 isc)139*4882a593Smuzhiyun static inline int zpci_set_irq_ctrl(u16 ctl, u8 isc)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun union zpci_sic_iib iib = {{0}};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun return __zpci_set_irq_ctrl(ctl, isc, &iib);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun #endif
147