1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2015 Regents of the University of California
4*4882a593Smuzhiyun * Copyright (C) 2017 SiFive
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef _ASM_RISCV_SPINLOCK_H
8*4882a593Smuzhiyun #define _ASM_RISCV_SPINLOCK_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <asm/current.h>
12*4882a593Smuzhiyun #include <asm/fence.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * Simple spin lock operations. These provide no fairness guarantees.
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* FIXME: Replace this with a ticket lock, like MIPS. */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
21*4882a593Smuzhiyun
arch_spin_unlock(arch_spinlock_t * lock)22*4882a593Smuzhiyun static inline void arch_spin_unlock(arch_spinlock_t *lock)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun smp_store_release(&lock->lock, 0);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
arch_spin_trylock(arch_spinlock_t * lock)27*4882a593Smuzhiyun static inline int arch_spin_trylock(arch_spinlock_t *lock)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun int tmp = 1, busy;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun __asm__ __volatile__ (
32*4882a593Smuzhiyun " amoswap.w %0, %2, %1\n"
33*4882a593Smuzhiyun RISCV_ACQUIRE_BARRIER
34*4882a593Smuzhiyun : "=r" (busy), "+A" (lock->lock)
35*4882a593Smuzhiyun : "r" (tmp)
36*4882a593Smuzhiyun : "memory");
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return !busy;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
arch_spin_lock(arch_spinlock_t * lock)41*4882a593Smuzhiyun static inline void arch_spin_lock(arch_spinlock_t *lock)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun while (1) {
44*4882a593Smuzhiyun if (arch_spin_is_locked(lock))
45*4882a593Smuzhiyun continue;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (arch_spin_trylock(lock))
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /***********************************************************/
53*4882a593Smuzhiyun
arch_read_lock(arch_rwlock_t * lock)54*4882a593Smuzhiyun static inline void arch_read_lock(arch_rwlock_t *lock)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun int tmp;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun __asm__ __volatile__(
59*4882a593Smuzhiyun "1: lr.w %1, %0\n"
60*4882a593Smuzhiyun " bltz %1, 1b\n"
61*4882a593Smuzhiyun " addi %1, %1, 1\n"
62*4882a593Smuzhiyun " sc.w %1, %1, %0\n"
63*4882a593Smuzhiyun " bnez %1, 1b\n"
64*4882a593Smuzhiyun RISCV_ACQUIRE_BARRIER
65*4882a593Smuzhiyun : "+A" (lock->lock), "=&r" (tmp)
66*4882a593Smuzhiyun :: "memory");
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
arch_write_lock(arch_rwlock_t * lock)69*4882a593Smuzhiyun static inline void arch_write_lock(arch_rwlock_t *lock)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int tmp;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun __asm__ __volatile__(
74*4882a593Smuzhiyun "1: lr.w %1, %0\n"
75*4882a593Smuzhiyun " bnez %1, 1b\n"
76*4882a593Smuzhiyun " li %1, -1\n"
77*4882a593Smuzhiyun " sc.w %1, %1, %0\n"
78*4882a593Smuzhiyun " bnez %1, 1b\n"
79*4882a593Smuzhiyun RISCV_ACQUIRE_BARRIER
80*4882a593Smuzhiyun : "+A" (lock->lock), "=&r" (tmp)
81*4882a593Smuzhiyun :: "memory");
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
arch_read_trylock(arch_rwlock_t * lock)84*4882a593Smuzhiyun static inline int arch_read_trylock(arch_rwlock_t *lock)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun int busy;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun __asm__ __volatile__(
89*4882a593Smuzhiyun "1: lr.w %1, %0\n"
90*4882a593Smuzhiyun " bltz %1, 1f\n"
91*4882a593Smuzhiyun " addi %1, %1, 1\n"
92*4882a593Smuzhiyun " sc.w %1, %1, %0\n"
93*4882a593Smuzhiyun " bnez %1, 1b\n"
94*4882a593Smuzhiyun RISCV_ACQUIRE_BARRIER
95*4882a593Smuzhiyun "1:\n"
96*4882a593Smuzhiyun : "+A" (lock->lock), "=&r" (busy)
97*4882a593Smuzhiyun :: "memory");
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return !busy;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
arch_write_trylock(arch_rwlock_t * lock)102*4882a593Smuzhiyun static inline int arch_write_trylock(arch_rwlock_t *lock)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun int busy;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun __asm__ __volatile__(
107*4882a593Smuzhiyun "1: lr.w %1, %0\n"
108*4882a593Smuzhiyun " bnez %1, 1f\n"
109*4882a593Smuzhiyun " li %1, -1\n"
110*4882a593Smuzhiyun " sc.w %1, %1, %0\n"
111*4882a593Smuzhiyun " bnez %1, 1b\n"
112*4882a593Smuzhiyun RISCV_ACQUIRE_BARRIER
113*4882a593Smuzhiyun "1:\n"
114*4882a593Smuzhiyun : "+A" (lock->lock), "=&r" (busy)
115*4882a593Smuzhiyun :: "memory");
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return !busy;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
arch_read_unlock(arch_rwlock_t * lock)120*4882a593Smuzhiyun static inline void arch_read_unlock(arch_rwlock_t *lock)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun __asm__ __volatile__(
123*4882a593Smuzhiyun RISCV_RELEASE_BARRIER
124*4882a593Smuzhiyun " amoadd.w x0, %1, %0\n"
125*4882a593Smuzhiyun : "+A" (lock->lock)
126*4882a593Smuzhiyun : "r" (-1)
127*4882a593Smuzhiyun : "memory");
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
arch_write_unlock(arch_rwlock_t * lock)130*4882a593Smuzhiyun static inline void arch_write_unlock(arch_rwlock_t *lock)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun smp_store_release(&lock->lock, 0);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #endif /* _ASM_RISCV_SPINLOCK_H */
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