1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2019 SiFive
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _ASM_RISCV_SET_MEMORY_H
7*4882a593Smuzhiyun #define _ASM_RISCV_SET_MEMORY_H
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __ASSEMBLY__
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun * Functions to change memory attributes.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #ifdef CONFIG_MMU
14*4882a593Smuzhiyun int set_memory_ro(unsigned long addr, int numpages);
15*4882a593Smuzhiyun int set_memory_rw(unsigned long addr, int numpages);
16*4882a593Smuzhiyun int set_memory_x(unsigned long addr, int numpages);
17*4882a593Smuzhiyun int set_memory_nx(unsigned long addr, int numpages);
18*4882a593Smuzhiyun #else
set_memory_ro(unsigned long addr,int numpages)19*4882a593Smuzhiyun static inline int set_memory_ro(unsigned long addr, int numpages) { return 0; }
set_memory_rw(unsigned long addr,int numpages)20*4882a593Smuzhiyun static inline int set_memory_rw(unsigned long addr, int numpages) { return 0; }
set_memory_x(unsigned long addr,int numpages)21*4882a593Smuzhiyun static inline int set_memory_x(unsigned long addr, int numpages) { return 0; }
set_memory_nx(unsigned long addr,int numpages)22*4882a593Smuzhiyun static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }
23*4882a593Smuzhiyun #endif
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun int set_direct_map_invalid_noflush(struct page *page);
26*4882a593Smuzhiyun int set_direct_map_default_noflush(struct page *page);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
31*4882a593Smuzhiyun #ifdef CONFIG_64BIT
32*4882a593Smuzhiyun #define SECTION_ALIGN (1 << 21)
33*4882a593Smuzhiyun #else
34*4882a593Smuzhiyun #define SECTION_ALIGN (1 << 22)
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun #else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
37*4882a593Smuzhiyun #define SECTION_ALIGN L1_CACHE_BYTES
38*4882a593Smuzhiyun #endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #endif /* _ASM_RISCV_SET_MEMORY_H */
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