1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef _ASM_RISCV_IMAGE_H 4*4882a593Smuzhiyun #define _ASM_RISCV_IMAGE_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define RISCV_IMAGE_MAGIC "RISCV\0\0\0" 7*4882a593Smuzhiyun #define RISCV_IMAGE_MAGIC2 "RSC\x05" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RISCV_IMAGE_FLAG_BE_SHIFT 0 10*4882a593Smuzhiyun #define RISCV_IMAGE_FLAG_BE_MASK 0x1 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define RISCV_IMAGE_FLAG_LE 0 13*4882a593Smuzhiyun #define RISCV_IMAGE_FLAG_BE 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifdef CONFIG_CPU_BIG_ENDIAN 16*4882a593Smuzhiyun #error conversion of header fields to LE not yet implemented 17*4882a593Smuzhiyun #else 18*4882a593Smuzhiyun #define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ 22*4882a593Smuzhiyun RISCV_IMAGE_FLAG_##field##_SHIFT) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define __HEAD_FLAGS (__HEAD_FLAG(BE)) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define RISCV_HEADER_VERSION_MAJOR 0 27*4882a593Smuzhiyun #define RISCV_HEADER_VERSION_MINOR 2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \ 30*4882a593Smuzhiyun RISCV_HEADER_VERSION_MINOR) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 33*4882a593Smuzhiyun /** 34*4882a593Smuzhiyun * struct riscv_image_header - riscv kernel image header 35*4882a593Smuzhiyun * @code0: Executable code 36*4882a593Smuzhiyun * @code1: Executable code 37*4882a593Smuzhiyun * @text_offset: Image load offset (little endian) 38*4882a593Smuzhiyun * @image_size: Effective Image size (little endian) 39*4882a593Smuzhiyun * @flags: kernel flags (little endian) 40*4882a593Smuzhiyun * @version: version 41*4882a593Smuzhiyun * @res1: reserved 42*4882a593Smuzhiyun * @res2: reserved 43*4882a593Smuzhiyun * @magic: Magic number (RISC-V specific; deprecated) 44*4882a593Smuzhiyun * @magic2: Magic number 2 (to match the ARM64 'magic' field pos) 45*4882a593Smuzhiyun * @res3: reserved (will be used for PE COFF offset) 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * The intention is for this header format to be shared between multiple 48*4882a593Smuzhiyun * architectures to avoid a proliferation of image header formats. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct riscv_image_header { 52*4882a593Smuzhiyun u32 code0; 53*4882a593Smuzhiyun u32 code1; 54*4882a593Smuzhiyun u64 text_offset; 55*4882a593Smuzhiyun u64 image_size; 56*4882a593Smuzhiyun u64 flags; 57*4882a593Smuzhiyun u32 version; 58*4882a593Smuzhiyun u32 res1; 59*4882a593Smuzhiyun u64 res2; 60*4882a593Smuzhiyun u64 magic; 61*4882a593Smuzhiyun u32 magic2; 62*4882a593Smuzhiyun u32 res3; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 65*4882a593Smuzhiyun #endif /* _ASM_RISCV_IMAGE_H */ 66