1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copied from arch/arm64/include/asm/hwcap.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 ARM Ltd. 6*4882a593Smuzhiyun * Copyright (C) 2017 SiFive 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _ASM_RISCV_HWCAP_H 9*4882a593Smuzhiyun #define _ASM_RISCV_HWCAP_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bits.h> 12*4882a593Smuzhiyun #include <uapi/asm/hwcap.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * This yields a mask that user programs can use to figure out what 17*4882a593Smuzhiyun * instruction set this cpu supports. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define ELF_HWCAP (elf_hwcap) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum { 22*4882a593Smuzhiyun CAP_HWCAP = 1, 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun extern unsigned long elf_hwcap; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define RISCV_ISA_EXT_a ('a' - 'a') 28*4882a593Smuzhiyun #define RISCV_ISA_EXT_c ('c' - 'a') 29*4882a593Smuzhiyun #define RISCV_ISA_EXT_d ('d' - 'a') 30*4882a593Smuzhiyun #define RISCV_ISA_EXT_f ('f' - 'a') 31*4882a593Smuzhiyun #define RISCV_ISA_EXT_h ('h' - 'a') 32*4882a593Smuzhiyun #define RISCV_ISA_EXT_i ('i' - 'a') 33*4882a593Smuzhiyun #define RISCV_ISA_EXT_m ('m' - 'a') 34*4882a593Smuzhiyun #define RISCV_ISA_EXT_s ('s' - 'a') 35*4882a593Smuzhiyun #define RISCV_ISA_EXT_u ('u' - 'a') 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define RISCV_ISA_EXT_MAX 64 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); 44*4882a593Smuzhiyun #define riscv_isa_extension_available(isa_bitmap, ext) \ 45*4882a593Smuzhiyun __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif /* _ASM_RISCV_HWCAP_H */ 50