1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 Google, Inc 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_RISCV_CLINT_H 7*4882a593Smuzhiyun #define _ASM_RISCV_CLINT_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun #include <asm/mmio.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifdef CONFIG_RISCV_M_MODE 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * This lives in the CLINT driver, but is accessed directly by timex.h to avoid 15*4882a593Smuzhiyun * any overhead when accessing the MMIO timer. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * The ISA defines mtime as a 64-bit memory-mapped register that increments at 18*4882a593Smuzhiyun * a constant frequency, but it doesn't define some other constraints we depend 19*4882a593Smuzhiyun * on (most notably ordering constraints, but also some simpler stuff like the 20*4882a593Smuzhiyun * memory layout). Thus, this is called "clint_time_val" instead of something 21*4882a593Smuzhiyun * like "riscv_mtime", to signify that these non-ISA assumptions must hold. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun extern u64 __iomem *clint_time_val; 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif 27