1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2015 Regents of the University of California
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _ASM_RISCV_CACHEFLUSH_H
7*4882a593Smuzhiyun #define _ASM_RISCV_CACHEFLUSH_H
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/mm.h>
10*4882a593Smuzhiyun
local_flush_icache_all(void)11*4882a593Smuzhiyun static inline void local_flush_icache_all(void)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun asm volatile ("fence.i" ::: "memory");
14*4882a593Smuzhiyun }
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define PG_dcache_clean PG_arch_1
17*4882a593Smuzhiyun
flush_dcache_page(struct page * page)18*4882a593Smuzhiyun static inline void flush_dcache_page(struct page *page)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun if (test_bit(PG_dcache_clean, &page->flags))
21*4882a593Smuzhiyun clear_bit(PG_dcache_clean, &page->flags);
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * RISC-V doesn't have an instruction to flush parts of the instruction cache,
27*4882a593Smuzhiyun * so instead we just flush the whole thing.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun #define flush_icache_range(start, end) flush_icache_all()
30*4882a593Smuzhiyun #define flush_icache_user_page(vma, pg, addr, len) \
31*4882a593Smuzhiyun flush_icache_mm(vma->vm_mm, 0)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #ifndef CONFIG_SMP
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define flush_icache_all() local_flush_icache_all()
36*4882a593Smuzhiyun #define flush_icache_mm(mm, local) flush_icache_all()
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #else /* CONFIG_SMP */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun void flush_icache_all(void);
41*4882a593Smuzhiyun void flush_icache_mm(struct mm_struct *mm, bool local);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #endif /* CONFIG_SMP */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * Bits in sys_riscv_flush_icache()'s flags argument.
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
49*4882a593Smuzhiyun #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #include <asm-generic/cacheflush.h>
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #endif /* _ASM_RISCV_CACHEFLUSH_H */
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