1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Chen Liqin <liqin.chen@sunplusct.com> 4*4882a593Smuzhiyun * Copyright (C) 2012 Regents of the University of California 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_RISCV_CACHE_H 8*4882a593Smuzhiyun #define _ASM_RISCV_CACHE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define L1_CACHE_SHIFT 6 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that 16*4882a593Smuzhiyun * the flat loader aligns it accordingly. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #ifndef CONFIG_MMU 19*4882a593Smuzhiyun #define ARCH_SLAB_MINALIGN 16 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* _ASM_RISCV_CACHE_H */ 23