1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Tony Li <tony.li@freescale.com> 6*4882a593Smuzhiyun * Jason Jin <Jason.jin@freescale.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _POWERPC_SYSDEV_FSL_MSI_H 9*4882a593Smuzhiyun #define _POWERPC_SYSDEV_FSL_MSI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/of.h> 12*4882a593Smuzhiyun #include <asm/msi_bitmap.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */ 15*4882a593Smuzhiyun #define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */ 16*4882a593Smuzhiyun #define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1 17*4882a593Smuzhiyun #define IRQS_PER_MSI_REG 32 18*4882a593Smuzhiyun #define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define FSL_PIC_IP_MASK 0x0000000F 21*4882a593Smuzhiyun #define FSL_PIC_IP_MPIC 0x00000001 22*4882a593Smuzhiyun #define FSL_PIC_IP_IPIC 0x00000002 23*4882a593Smuzhiyun #define FSL_PIC_IP_VMPIC 0x00000003 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define MSI_HW_ERRATA_ENDIAN 0x00000010 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct fsl_msi_cascade_data; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct fsl_msi { 30*4882a593Smuzhiyun struct irq_domain *irqhost; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun unsigned long cascade_irq; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */ 35*4882a593Smuzhiyun u32 ibs_shift; /* Shift of interrupt bit select */ 36*4882a593Smuzhiyun u32 srs_shift; /* Shift of the shared interrupt register select */ 37*4882a593Smuzhiyun void __iomem *msi_regs; 38*4882a593Smuzhiyun u32 feature; 39*4882a593Smuzhiyun struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX]; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct msi_bitmap bitmap; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct list_head list; /* support multiple MSI banks */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun phandle phandle; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* _POWERPC_SYSDEV_FSL_MSI_H */ 49*4882a593Smuzhiyun 50