1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2009-2010 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Simple memory allocator abstraction for QorIQ (P1/P2) based Cache-SRAM
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is derived from the original work done
10*4882a593Smuzhiyun * by Sylvain Munaut for the Bestcomm SRAM allocator.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/export.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/of_platform.h>
18*4882a593Smuzhiyun #include <linux/pgtable.h>
19*4882a593Smuzhiyun #include <asm/fsl_85xx_cache_sram.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "fsl_85xx_cache_ctlr.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct mpc85xx_cache_sram *cache_sram;
24*4882a593Smuzhiyun
mpc85xx_cache_sram_alloc(unsigned int size,phys_addr_t * phys,unsigned int align)25*4882a593Smuzhiyun void *mpc85xx_cache_sram_alloc(unsigned int size,
26*4882a593Smuzhiyun phys_addr_t *phys, unsigned int align)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun unsigned long offset;
29*4882a593Smuzhiyun unsigned long flags;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (unlikely(cache_sram == NULL))
32*4882a593Smuzhiyun return NULL;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (!size || (size > cache_sram->size) || (align > cache_sram->size)) {
35*4882a593Smuzhiyun pr_err("%s(): size(=%x) or align(=%x) zero or too big\n",
36*4882a593Smuzhiyun __func__, size, align);
37*4882a593Smuzhiyun return NULL;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if ((align & (align - 1)) || align <= 1) {
41*4882a593Smuzhiyun pr_err("%s(): align(=%x) must be power of two and >1\n",
42*4882a593Smuzhiyun __func__, align);
43*4882a593Smuzhiyun return NULL;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun spin_lock_irqsave(&cache_sram->lock, flags);
47*4882a593Smuzhiyun offset = rh_alloc_align(cache_sram->rh, size, align, NULL);
48*4882a593Smuzhiyun spin_unlock_irqrestore(&cache_sram->lock, flags);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (IS_ERR_VALUE(offset))
51*4882a593Smuzhiyun return NULL;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun *phys = cache_sram->base_phys + offset;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return (unsigned char *)cache_sram->base_virt + offset;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun EXPORT_SYMBOL(mpc85xx_cache_sram_alloc);
58*4882a593Smuzhiyun
mpc85xx_cache_sram_free(void * ptr)59*4882a593Smuzhiyun void mpc85xx_cache_sram_free(void *ptr)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun unsigned long flags;
62*4882a593Smuzhiyun BUG_ON(!ptr);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun spin_lock_irqsave(&cache_sram->lock, flags);
65*4882a593Smuzhiyun rh_free(cache_sram->rh, ptr - cache_sram->base_virt);
66*4882a593Smuzhiyun spin_unlock_irqrestore(&cache_sram->lock, flags);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun EXPORT_SYMBOL(mpc85xx_cache_sram_free);
69*4882a593Smuzhiyun
instantiate_cache_sram(struct platform_device * dev,struct sram_parameters sram_params)70*4882a593Smuzhiyun int __init instantiate_cache_sram(struct platform_device *dev,
71*4882a593Smuzhiyun struct sram_parameters sram_params)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun int ret = 0;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (cache_sram) {
76*4882a593Smuzhiyun dev_err(&dev->dev, "Already initialized cache-sram\n");
77*4882a593Smuzhiyun return -EBUSY;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun cache_sram = kzalloc(sizeof(struct mpc85xx_cache_sram), GFP_KERNEL);
81*4882a593Smuzhiyun if (!cache_sram) {
82*4882a593Smuzhiyun dev_err(&dev->dev, "Out of memory for cache_sram structure\n");
83*4882a593Smuzhiyun return -ENOMEM;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun cache_sram->base_phys = sram_params.sram_offset;
87*4882a593Smuzhiyun cache_sram->size = sram_params.sram_size;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (!request_mem_region(cache_sram->base_phys, cache_sram->size,
90*4882a593Smuzhiyun "fsl_85xx_cache_sram")) {
91*4882a593Smuzhiyun dev_err(&dev->dev, "%pOF: request memory failed\n",
92*4882a593Smuzhiyun dev->dev.of_node);
93*4882a593Smuzhiyun ret = -ENXIO;
94*4882a593Smuzhiyun goto out_free;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun cache_sram->base_virt = ioremap_coherent(cache_sram->base_phys,
98*4882a593Smuzhiyun cache_sram->size);
99*4882a593Smuzhiyun if (!cache_sram->base_virt) {
100*4882a593Smuzhiyun dev_err(&dev->dev, "%pOF: ioremap_coherent failed\n",
101*4882a593Smuzhiyun dev->dev.of_node);
102*4882a593Smuzhiyun ret = -ENOMEM;
103*4882a593Smuzhiyun goto out_release;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun cache_sram->rh = rh_create(sizeof(unsigned int));
107*4882a593Smuzhiyun if (IS_ERR(cache_sram->rh)) {
108*4882a593Smuzhiyun dev_err(&dev->dev, "%pOF: Unable to create remote heap\n",
109*4882a593Smuzhiyun dev->dev.of_node);
110*4882a593Smuzhiyun ret = PTR_ERR(cache_sram->rh);
111*4882a593Smuzhiyun goto out_unmap;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun rh_attach_region(cache_sram->rh, 0, cache_sram->size);
115*4882a593Smuzhiyun spin_lock_init(&cache_sram->lock);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun dev_info(&dev->dev, "[base:0x%llx, size:0x%x] configured and loaded\n",
118*4882a593Smuzhiyun (unsigned long long)cache_sram->base_phys, cache_sram->size);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun out_unmap:
123*4882a593Smuzhiyun iounmap(cache_sram->base_virt);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun out_release:
126*4882a593Smuzhiyun release_mem_region(cache_sram->base_phys, cache_sram->size);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun out_free:
129*4882a593Smuzhiyun kfree(cache_sram);
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
remove_cache_sram(struct platform_device * dev)133*4882a593Smuzhiyun void remove_cache_sram(struct platform_device *dev)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun BUG_ON(!cache_sram);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun rh_detach_region(cache_sram->rh, 0, cache_sram->size);
138*4882a593Smuzhiyun rh_destroy(cache_sram->rh);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun iounmap(cache_sram->base_virt);
141*4882a593Smuzhiyun release_mem_region(cache_sram->base_phys, cache_sram->size);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun kfree(cache_sram);
144*4882a593Smuzhiyun cache_sram = NULL;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun dev_info(&dev->dev, "MPC85xx Cache-SRAM driver unloaded\n");
147*4882a593Smuzhiyun }
148