1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2014-2016 IBM Corp.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <asm/pnv-pci.h>
8*4882a593Smuzhiyun #include <asm/opal.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "pci.h"
11*4882a593Smuzhiyun
pnv_phb_to_cxl_mode(struct pci_dev * dev,uint64_t mode)12*4882a593Smuzhiyun int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun struct pci_controller *hose = pci_bus_to_host(dev->bus);
15*4882a593Smuzhiyun struct pnv_phb *phb = hose->private_data;
16*4882a593Smuzhiyun struct pnv_ioda_pe *pe;
17*4882a593Smuzhiyun int rc;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun pe = pnv_ioda_get_pe(dev);
20*4882a593Smuzhiyun if (!pe)
21*4882a593Smuzhiyun return -ENODEV;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun pe_info(pe, "Switching PHB to CXL\n");
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
26*4882a593Smuzhiyun if (rc == OPAL_UNSUPPORTED)
27*4882a593Smuzhiyun dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
28*4882a593Smuzhiyun else if (rc)
29*4882a593Smuzhiyun dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return rc;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Find PHB for cxl dev and allocate MSI hwirqs?
36*4882a593Smuzhiyun * Returns the absolute hardware IRQ number
37*4882a593Smuzhiyun */
pnv_cxl_alloc_hwirqs(struct pci_dev * dev,int num)38*4882a593Smuzhiyun int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct pci_controller *hose = pci_bus_to_host(dev->bus);
41*4882a593Smuzhiyun struct pnv_phb *phb = hose->private_data;
42*4882a593Smuzhiyun int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun if (hwirq < 0) {
45*4882a593Smuzhiyun dev_warn(&dev->dev, "Failed to find a free MSI\n");
46*4882a593Smuzhiyun return -ENOSPC;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return phb->msi_base + hwirq;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
52*4882a593Smuzhiyun
pnv_cxl_release_hwirqs(struct pci_dev * dev,int hwirq,int num)53*4882a593Smuzhiyun void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct pci_controller *hose = pci_bus_to_host(dev->bus);
56*4882a593Smuzhiyun struct pnv_phb *phb = hose->private_data;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
61*4882a593Smuzhiyun
pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges * irqs,struct pci_dev * dev)62*4882a593Smuzhiyun void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
63*4882a593Smuzhiyun struct pci_dev *dev)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct pci_controller *hose = pci_bus_to_host(dev->bus);
66*4882a593Smuzhiyun struct pnv_phb *phb = hose->private_data;
67*4882a593Smuzhiyun int i, hwirq;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun for (i = 1; i < CXL_IRQ_RANGES; i++) {
70*4882a593Smuzhiyun if (!irqs->range[i])
71*4882a593Smuzhiyun continue;
72*4882a593Smuzhiyun pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
73*4882a593Smuzhiyun i, irqs->offset[i],
74*4882a593Smuzhiyun irqs->range[i]);
75*4882a593Smuzhiyun hwirq = irqs->offset[i] - phb->msi_base;
76*4882a593Smuzhiyun msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
77*4882a593Smuzhiyun irqs->range[i]);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
81*4882a593Smuzhiyun
pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges * irqs,struct pci_dev * dev,int num)82*4882a593Smuzhiyun int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
83*4882a593Smuzhiyun struct pci_dev *dev, int num)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct pci_controller *hose = pci_bus_to_host(dev->bus);
86*4882a593Smuzhiyun struct pnv_phb *phb = hose->private_data;
87*4882a593Smuzhiyun int i, hwirq, try;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun memset(irqs, 0, sizeof(struct cxl_irq_ranges));
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* 0 is reserved for the multiplexed PSL DSI interrupt */
92*4882a593Smuzhiyun for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
93*4882a593Smuzhiyun try = num;
94*4882a593Smuzhiyun while (try) {
95*4882a593Smuzhiyun hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
96*4882a593Smuzhiyun if (hwirq >= 0)
97*4882a593Smuzhiyun break;
98*4882a593Smuzhiyun try /= 2;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun if (!try)
101*4882a593Smuzhiyun goto fail;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun irqs->offset[i] = phb->msi_base + hwirq;
104*4882a593Smuzhiyun irqs->range[i] = try;
105*4882a593Smuzhiyun pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
106*4882a593Smuzhiyun i, irqs->offset[i], irqs->range[i]);
107*4882a593Smuzhiyun num -= try;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun if (num)
110*4882a593Smuzhiyun goto fail;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return 0;
113*4882a593Smuzhiyun fail:
114*4882a593Smuzhiyun pnv_cxl_release_hwirq_ranges(irqs, dev);
115*4882a593Smuzhiyun return -ENOSPC;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
118*4882a593Smuzhiyun
pnv_cxl_get_irq_count(struct pci_dev * dev)119*4882a593Smuzhiyun int pnv_cxl_get_irq_count(struct pci_dev *dev)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct pci_controller *hose = pci_bus_to_host(dev->bus);
122*4882a593Smuzhiyun struct pnv_phb *phb = hose->private_data;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return phb->msi_bmp.irq_count;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun EXPORT_SYMBOL(pnv_cxl_get_irq_count);
127*4882a593Smuzhiyun
pnv_cxl_ioda_msi_setup(struct pci_dev * dev,unsigned int hwirq,unsigned int virq)128*4882a593Smuzhiyun int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
129*4882a593Smuzhiyun unsigned int virq)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun struct pci_controller *hose = pci_bus_to_host(dev->bus);
132*4882a593Smuzhiyun struct pnv_phb *phb = hose->private_data;
133*4882a593Smuzhiyun unsigned int xive_num = hwirq - phb->msi_base;
134*4882a593Smuzhiyun struct pnv_ioda_pe *pe;
135*4882a593Smuzhiyun int rc;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (!(pe = pnv_ioda_get_pe(dev)))
138*4882a593Smuzhiyun return -ENODEV;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Assign XIVE to PE */
141*4882a593Smuzhiyun rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
142*4882a593Smuzhiyun if (rc) {
143*4882a593Smuzhiyun pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
144*4882a593Smuzhiyun "hwirq 0x%x XIVE 0x%x PE\n",
145*4882a593Smuzhiyun pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
146*4882a593Smuzhiyun return -EIO;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun pnv_set_msi_irq_chip(phb, virq);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun #if IS_MODULE(CONFIG_CXL)
get_cxl_module(void)155*4882a593Smuzhiyun static inline int get_cxl_module(void)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun struct module *cxl_module;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun mutex_lock(&module_mutex);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun cxl_module = find_module("cxl");
162*4882a593Smuzhiyun if (cxl_module)
163*4882a593Smuzhiyun __module_get(cxl_module);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun mutex_unlock(&module_mutex);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun if (!cxl_module)
168*4882a593Smuzhiyun return -ENODEV;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun #else
get_cxl_module(void)173*4882a593Smuzhiyun static inline int get_cxl_module(void) { return 0; }
174*4882a593Smuzhiyun #endif
175