1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2006-2007 PA Semi, Inc 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Maintained by: Olof Johansson <olof@lixom.net> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <asm/processor.h> 9*4882a593Smuzhiyun#include <asm/page.h> 10*4882a593Smuzhiyun#include <asm/ppc_asm.h> 11*4882a593Smuzhiyun#include <asm/cputable.h> 12*4882a593Smuzhiyun#include <asm/cache.h> 13*4882a593Smuzhiyun#include <asm/thread_info.h> 14*4882a593Smuzhiyun#include <asm/asm-offsets.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/* Power savings opcodes since not all binutils have them at this time */ 17*4882a593Smuzhiyun#define DOZE .long 0x4c000324 18*4882a593Smuzhiyun#define NAP .long 0x4c000364 19*4882a593Smuzhiyun#define SLEEP .long 0x4c0003a4 20*4882a593Smuzhiyun#define RVW .long 0x4c0003e4 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun/* Common sequence to do before going to any of the 23*4882a593Smuzhiyun * powersavings modes. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun#define PRE_SLEEP_SEQUENCE \ 27*4882a593Smuzhiyun std r3,8(r1); \ 28*4882a593Smuzhiyun ptesync ; \ 29*4882a593Smuzhiyun ld r3,8(r1); \ 30*4882a593Smuzhiyun1: cmpd r3,r3; \ 31*4882a593Smuzhiyun bne 1b 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun_doze: 34*4882a593Smuzhiyun PRE_SLEEP_SEQUENCE 35*4882a593Smuzhiyun DOZE 36*4882a593Smuzhiyun b . 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun_GLOBAL(idle_spin) 40*4882a593Smuzhiyun blr 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun_GLOBAL(idle_doze) 43*4882a593Smuzhiyun LOAD_REG_ADDR(r3, _doze) 44*4882a593Smuzhiyun b sleep_common 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun/* Add more modes here later */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunsleep_common: 49*4882a593Smuzhiyun mflr r0 50*4882a593Smuzhiyun std r0, 16(r1) 51*4882a593Smuzhiyun stdu r1,-64(r1) 52*4882a593Smuzhiyun#ifdef CONFIG_PPC_PASEMI_CPUFREQ 53*4882a593Smuzhiyun std r3, 48(r1) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Only do power savings when in astate 0 */ 56*4882a593Smuzhiyun bl check_astate 57*4882a593Smuzhiyun cmpwi r3,0 58*4882a593Smuzhiyun bne 1f 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ld r3, 48(r1) 61*4882a593Smuzhiyun#endif 62*4882a593Smuzhiyun LOAD_REG_IMMEDIATE(r6,MSR_DR|MSR_IR|MSR_ME|MSR_EE) 63*4882a593Smuzhiyun mfmsr r4 64*4882a593Smuzhiyun andc r5,r4,r6 65*4882a593Smuzhiyun mtmsrd r5,0 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun mtctr r3 68*4882a593Smuzhiyun bctrl 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun mtmsrd r4,0 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun1: addi r1,r1,64 73*4882a593Smuzhiyun ld r0,16(r1) 74*4882a593Smuzhiyun mtlr r0 75*4882a593Smuzhiyun blr 76*4882a593Smuzhiyun 77