1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Board setup routines for the Motorola/Emerson MVME5100.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2013 CSC Australia Pty. Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on earlier code by:
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Matt Porter, MontaVista Software Inc.
10*4882a593Smuzhiyun * Copyright 2001 MontaVista Software Inc.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Author: Stephen Chivers <schivers@csc.com>
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/of_platform.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/i8259.h>
18*4882a593Smuzhiyun #include <asm/pci-bridge.h>
19*4882a593Smuzhiyun #include <asm/mpic.h>
20*4882a593Smuzhiyun #include <asm/prom.h>
21*4882a593Smuzhiyun #include <mm/mmu_decl.h>
22*4882a593Smuzhiyun #include <asm/udbg.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define HAWK_MPIC_SIZE 0x00040000U
25*4882a593Smuzhiyun #define MVME5100_PCI_MEM_OFFSET 0x00000000
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Board register addresses. */
28*4882a593Smuzhiyun #define BOARD_STATUS_REG 0xfef88080
29*4882a593Smuzhiyun #define BOARD_MODFAIL_REG 0xfef88090
30*4882a593Smuzhiyun #define BOARD_MODRST_REG 0xfef880a0
31*4882a593Smuzhiyun #define BOARD_TBEN_REG 0xfef880c0
32*4882a593Smuzhiyun #define BOARD_SW_READ_REG 0xfef880e0
33*4882a593Smuzhiyun #define BOARD_GEO_ADDR_REG 0xfef880e8
34*4882a593Smuzhiyun #define BOARD_EXT_FEATURE1_REG 0xfef880f0
35*4882a593Smuzhiyun #define BOARD_EXT_FEATURE2_REG 0xfef88100
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static phys_addr_t pci_membase;
38*4882a593Smuzhiyun static u_char *restart;
39*4882a593Smuzhiyun
mvme5100_8259_cascade(struct irq_desc * desc)40*4882a593Smuzhiyun static void mvme5100_8259_cascade(struct irq_desc *desc)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct irq_chip *chip = irq_desc_get_chip(desc);
43*4882a593Smuzhiyun unsigned int cascade_irq = i8259_irq();
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (cascade_irq)
46*4882a593Smuzhiyun generic_handle_irq(cascade_irq);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun chip->irq_eoi(&desc->irq_data);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
mvme5100_pic_init(void)51*4882a593Smuzhiyun static void __init mvme5100_pic_init(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct mpic *mpic;
54*4882a593Smuzhiyun struct device_node *np;
55*4882a593Smuzhiyun struct device_node *cp = NULL;
56*4882a593Smuzhiyun unsigned int cirq;
57*4882a593Smuzhiyun unsigned long intack = 0;
58*4882a593Smuzhiyun const u32 *prop = NULL;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun np = of_find_node_by_type(NULL, "open-pic");
61*4882a593Smuzhiyun if (!np) {
62*4882a593Smuzhiyun pr_err("Could not find open-pic node\n");
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun mpic = mpic_alloc(np, pci_membase, 0, 16, 256, " OpenPIC ");
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun BUG_ON(mpic == NULL);
69*4882a593Smuzhiyun of_node_put(np);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun mpic_assign_isu(mpic, 0, pci_membase + 0x10000);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun mpic_init(mpic);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun cp = of_find_compatible_node(NULL, NULL, "chrp,iic");
76*4882a593Smuzhiyun if (cp == NULL) {
77*4882a593Smuzhiyun pr_warn("mvme5100_pic_init: couldn't find i8259\n");
78*4882a593Smuzhiyun return;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun cirq = irq_of_parse_and_map(cp, 0);
82*4882a593Smuzhiyun if (!cirq) {
83*4882a593Smuzhiyun pr_warn("mvme5100_pic_init: no cascade interrupt?\n");
84*4882a593Smuzhiyun return;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun np = of_find_compatible_node(NULL, "pci", "mpc10x-pci");
88*4882a593Smuzhiyun if (np) {
89*4882a593Smuzhiyun prop = of_get_property(np, "8259-interrupt-acknowledge", NULL);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (prop)
92*4882a593Smuzhiyun intack = prop[0];
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun of_node_put(np);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (intack)
98*4882a593Smuzhiyun pr_debug("mvme5100_pic_init: PCI 8259 intack at 0x%016lx\n",
99*4882a593Smuzhiyun intack);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun i8259_init(cp, intack);
102*4882a593Smuzhiyun of_node_put(cp);
103*4882a593Smuzhiyun irq_set_chained_handler(cirq, mvme5100_8259_cascade);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
mvme5100_add_bridge(struct device_node * dev)106*4882a593Smuzhiyun static int __init mvme5100_add_bridge(struct device_node *dev)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun const int *bus_range;
109*4882a593Smuzhiyun int len;
110*4882a593Smuzhiyun struct pci_controller *hose;
111*4882a593Smuzhiyun unsigned short devid;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun pr_info("Adding PCI host bridge %pOF\n", dev);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun bus_range = of_get_property(dev, "bus-range", &len);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun hose = pcibios_alloc_controller(dev);
118*4882a593Smuzhiyun if (hose == NULL)
119*4882a593Smuzhiyun return -ENOMEM;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun hose->first_busno = bus_range ? bus_range[0] : 0;
122*4882a593Smuzhiyun hose->last_busno = bus_range ? bus_range[1] : 0xff;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun setup_indirect_pci(hose, 0xfe000cf8, 0xfe000cfc, 0);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun pci_process_bridge_OF_ranges(hose, dev, 1);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun early_read_config_word(hose, 0, 0, PCI_DEVICE_ID, &devid);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK) {
131*4882a593Smuzhiyun pr_err("HAWK PHB not present?\n");
132*4882a593Smuzhiyun return 0;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (pci_membase == 0) {
138*4882a593Smuzhiyun pr_err("HAWK PHB mibar not correctly set?\n");
139*4882a593Smuzhiyun return 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun pr_info("mvme5100_pic_init: pci_membase: %x\n", pci_membase);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const struct of_device_id mvme5100_of_bus_ids[] __initconst = {
148*4882a593Smuzhiyun { .compatible = "hawk-bridge", },
149*4882a593Smuzhiyun {},
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun * Setup the architecture
154*4882a593Smuzhiyun */
mvme5100_setup_arch(void)155*4882a593Smuzhiyun static void __init mvme5100_setup_arch(void)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun struct device_node *np;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun if (ppc_md.progress)
160*4882a593Smuzhiyun ppc_md.progress("mvme5100_setup_arch()", 0);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun for_each_compatible_node(np, "pci", "hawk-pci")
163*4882a593Smuzhiyun mvme5100_add_bridge(np);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun restart = ioremap(BOARD_MODRST_REG, 4);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun
mvme5100_show_cpuinfo(struct seq_file * m)169*4882a593Smuzhiyun static void mvme5100_show_cpuinfo(struct seq_file *m)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun seq_puts(m, "Vendor\t\t: Motorola/Emerson\n");
172*4882a593Smuzhiyun seq_puts(m, "Machine\t\t: MVME5100\n");
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
mvme5100_restart(char * cmd)175*4882a593Smuzhiyun static void __noreturn mvme5100_restart(char *cmd)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun local_irq_disable();
179*4882a593Smuzhiyun mtmsr(mfmsr() | MSR_IP);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun out_8((u_char *) restart, 0x01);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun while (1)
184*4882a593Smuzhiyun ;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /*
188*4882a593Smuzhiyun * Called very early, device-tree isn't unflattened
189*4882a593Smuzhiyun */
mvme5100_probe(void)190*4882a593Smuzhiyun static int __init mvme5100_probe(void)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun return of_machine_is_compatible("MVME5100");
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
probe_of_platform_devices(void)195*4882a593Smuzhiyun static int __init probe_of_platform_devices(void)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun of_platform_bus_probe(NULL, mvme5100_of_bus_ids, NULL);
199*4882a593Smuzhiyun return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun machine_device_initcall(mvme5100, probe_of_platform_devices);
203*4882a593Smuzhiyun
define_machine(mvme5100)204*4882a593Smuzhiyun define_machine(mvme5100) {
205*4882a593Smuzhiyun .name = "MVME5100",
206*4882a593Smuzhiyun .probe = mvme5100_probe,
207*4882a593Smuzhiyun .setup_arch = mvme5100_setup_arch,
208*4882a593Smuzhiyun .init_IRQ = mvme5100_pic_init,
209*4882a593Smuzhiyun .show_cpuinfo = mvme5100_show_cpuinfo,
210*4882a593Smuzhiyun .get_irq = mpic_get_irq,
211*4882a593Smuzhiyun .restart = mvme5100_restart,
212*4882a593Smuzhiyun .calibrate_decr = generic_calibrate_decr,
213*4882a593Smuzhiyun .progress = udbg_progress,
214*4882a593Smuzhiyun };
215