xref: /OK3568_Linux_fs/kernel/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * mpc7448_hpc2.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Board setup routines for the Freescale mpc7448hpc2(taiga) platform
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Jacob Pan
8*4882a593Smuzhiyun  *	 jacob.pan@freescale.com
9*4882a593Smuzhiyun  * Author: Xianghua Xiao
10*4882a593Smuzhiyun  *       x.xiao@freescale.com
11*4882a593Smuzhiyun  * Maintainer: Roy Zang <tie-fei.zang@freescale.com>
12*4882a593Smuzhiyun  * 	Add Flat Device Tree support fot mpc7448hpc2 board
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * Copyright 2004-2006 Freescale Semiconductor, Inc.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/stddef.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/pci.h>
20*4882a593Smuzhiyun #include <linux/kdev_t.h>
21*4882a593Smuzhiyun #include <linux/console.h>
22*4882a593Smuzhiyun #include <linux/extable.h>
23*4882a593Smuzhiyun #include <linux/delay.h>
24*4882a593Smuzhiyun #include <linux/irq.h>
25*4882a593Smuzhiyun #include <linux/seq_file.h>
26*4882a593Smuzhiyun #include <linux/root_dev.h>
27*4882a593Smuzhiyun #include <linux/serial.h>
28*4882a593Smuzhiyun #include <linux/tty.h>
29*4882a593Smuzhiyun #include <linux/serial_core.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <asm/time.h>
32*4882a593Smuzhiyun #include <asm/machdep.h>
33*4882a593Smuzhiyun #include <asm/prom.h>
34*4882a593Smuzhiyun #include <asm/udbg.h>
35*4882a593Smuzhiyun #include <asm/tsi108.h>
36*4882a593Smuzhiyun #include <asm/pci-bridge.h>
37*4882a593Smuzhiyun #include <asm/reg.h>
38*4882a593Smuzhiyun #include <mm/mmu_decl.h>
39*4882a593Smuzhiyun #include <asm/tsi108_pci.h>
40*4882a593Smuzhiyun #include <asm/tsi108_irq.h>
41*4882a593Smuzhiyun #include <asm/mpic.h>
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #undef DEBUG
44*4882a593Smuzhiyun #ifdef DEBUG
45*4882a593Smuzhiyun #define DBG(fmt...) do { printk(fmt); } while(0)
46*4882a593Smuzhiyun #else
47*4882a593Smuzhiyun #define DBG(fmt...) do { } while(0)
48*4882a593Smuzhiyun #endif
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define MPC7448HPC2_PCI_CFG_PHYS 0xfb000000
51*4882a593Smuzhiyun 
mpc7448_hpc2_exclude_device(struct pci_controller * hose,u_char bus,u_char devfn)52*4882a593Smuzhiyun int mpc7448_hpc2_exclude_device(struct pci_controller *hose,
53*4882a593Smuzhiyun 				u_char bus, u_char devfn)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	if (bus == 0 && PCI_SLOT(devfn) == 0)
56*4882a593Smuzhiyun 		return PCIBIOS_DEVICE_NOT_FOUND;
57*4882a593Smuzhiyun 	else
58*4882a593Smuzhiyun 		return PCIBIOS_SUCCESSFUL;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
mpc7448_hpc2_setup_arch(void)61*4882a593Smuzhiyun static void __init mpc7448_hpc2_setup_arch(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	struct device_node *np;
64*4882a593Smuzhiyun 	if (ppc_md.progress)
65*4882a593Smuzhiyun 		ppc_md.progress("mpc7448_hpc2_setup_arch():set_bridge", 0);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	tsi108_csr_vir_base = get_vir_csrbase();
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	/* setup PCI host bridge */
70*4882a593Smuzhiyun #ifdef CONFIG_PCI
71*4882a593Smuzhiyun 	for_each_compatible_node(np, "pci", "tsi108-pci")
72*4882a593Smuzhiyun 		tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0);
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
75*4882a593Smuzhiyun 	if (ppc_md.progress)
76*4882a593Smuzhiyun 		ppc_md.progress("tsi108: resources set", 0x100);
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	printk(KERN_INFO "MPC7448HPC2 (TAIGA) Platform\n");
80*4882a593Smuzhiyun 	printk(KERN_INFO
81*4882a593Smuzhiyun 	       "Jointly ported by Freescale and Tundra Semiconductor\n");
82*4882a593Smuzhiyun 	printk(KERN_INFO
83*4882a593Smuzhiyun 	       "Enabling L2 cache then enabling the HID0 prefetch engine.\n");
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun  * Interrupt setup and service.  Interrupts on the mpc7448_hpc2 come
88*4882a593Smuzhiyun  * from the four external INT pins, PCI interrupts are routed via
89*4882a593Smuzhiyun  * PCI interrupt control registers, it generates internal IRQ23
90*4882a593Smuzhiyun  *
91*4882a593Smuzhiyun  * Interrupt routing on the Taiga Board:
92*4882a593Smuzhiyun  * TSI108:PB_INT[0] -> CPU0:INT#
93*4882a593Smuzhiyun  * TSI108:PB_INT[1] -> CPU0:MCP#
94*4882a593Smuzhiyun  * TSI108:PB_INT[2] -> N/C
95*4882a593Smuzhiyun  * TSI108:PB_INT[3] -> N/C
96*4882a593Smuzhiyun  */
mpc7448_hpc2_init_IRQ(void)97*4882a593Smuzhiyun static void __init mpc7448_hpc2_init_IRQ(void)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	struct mpic *mpic;
100*4882a593Smuzhiyun #ifdef CONFIG_PCI
101*4882a593Smuzhiyun 	unsigned int cascade_pci_irq;
102*4882a593Smuzhiyun 	struct device_node *tsi_pci;
103*4882a593Smuzhiyun 	struct device_node *cascade_node = NULL;
104*4882a593Smuzhiyun #endif
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
107*4882a593Smuzhiyun 			MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
108*4882a593Smuzhiyun 			24, 0,
109*4882a593Smuzhiyun 			"Tsi108_PIC");
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	BUG_ON(mpic == NULL);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	mpic_init(mpic);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #ifdef CONFIG_PCI
118*4882a593Smuzhiyun 	tsi_pci = of_find_node_by_type(NULL, "pci");
119*4882a593Smuzhiyun 	if (tsi_pci == NULL) {
120*4882a593Smuzhiyun 		printk("%s: No tsi108 pci node found !\n", __func__);
121*4882a593Smuzhiyun 		return;
122*4882a593Smuzhiyun 	}
123*4882a593Smuzhiyun 	cascade_node = of_find_node_by_type(NULL, "pic-router");
124*4882a593Smuzhiyun 	if (cascade_node == NULL) {
125*4882a593Smuzhiyun 		printk("%s: No tsi108 pci cascade node found !\n", __func__);
126*4882a593Smuzhiyun 		return;
127*4882a593Smuzhiyun 	}
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
130*4882a593Smuzhiyun 	DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__,
131*4882a593Smuzhiyun 	    (u32) cascade_pci_irq);
132*4882a593Smuzhiyun 	tsi108_pci_int_init(cascade_node);
133*4882a593Smuzhiyun 	irq_set_handler_data(cascade_pci_irq, mpic);
134*4882a593Smuzhiyun 	irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
135*4882a593Smuzhiyun #endif
136*4882a593Smuzhiyun 	/* Configure MPIC outputs to CPU0 */
137*4882a593Smuzhiyun 	tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
mpc7448_hpc2_show_cpuinfo(struct seq_file * m)140*4882a593Smuzhiyun void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	seq_printf(m, "vendor\t\t: Freescale Semiconductor\n");
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun 
mpc7448_hpc2_restart(char * cmd)145*4882a593Smuzhiyun static void __noreturn mpc7448_hpc2_restart(char *cmd)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun 	local_irq_disable();
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* Set exception prefix high - to the firmware */
150*4882a593Smuzhiyun 	mtmsr(mfmsr() | MSR_IP);
151*4882a593Smuzhiyun 	isync();
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	for (;;) ;		/* Spin until reset happens */
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun /*
157*4882a593Smuzhiyun  * Called very early, device-tree isn't unflattened
158*4882a593Smuzhiyun  */
mpc7448_hpc2_probe(void)159*4882a593Smuzhiyun static int __init mpc7448_hpc2_probe(void)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	if (!of_machine_is_compatible("mpc74xx"))
162*4882a593Smuzhiyun 		return 0;
163*4882a593Smuzhiyun 	return 1;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
mpc7448_machine_check_exception(struct pt_regs * regs)166*4882a593Smuzhiyun static int mpc7448_machine_check_exception(struct pt_regs *regs)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	const struct exception_table_entry *entry;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	/* Are we prepared to handle this fault */
171*4882a593Smuzhiyun 	if ((entry = search_exception_tables(regs->nip)) != NULL) {
172*4882a593Smuzhiyun 		tsi108_clear_pci_cfg_error();
173*4882a593Smuzhiyun 		regs->msr |= MSR_RI;
174*4882a593Smuzhiyun 		regs->nip = extable_fixup(entry);
175*4882a593Smuzhiyun 		return 1;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 	return 0;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
define_machine(mpc7448_hpc2)180*4882a593Smuzhiyun define_machine(mpc7448_hpc2){
181*4882a593Smuzhiyun 	.name 			= "MPC7448 HPC2",
182*4882a593Smuzhiyun 	.probe 			= mpc7448_hpc2_probe,
183*4882a593Smuzhiyun 	.setup_arch 		= mpc7448_hpc2_setup_arch,
184*4882a593Smuzhiyun 	.init_IRQ 		= mpc7448_hpc2_init_IRQ,
185*4882a593Smuzhiyun 	.show_cpuinfo 		= mpc7448_hpc2_show_cpuinfo,
186*4882a593Smuzhiyun 	.get_irq 		= mpic_get_irq,
187*4882a593Smuzhiyun 	.restart 		= mpc7448_hpc2_restart,
188*4882a593Smuzhiyun 	.calibrate_decr 	= generic_calibrate_decr,
189*4882a593Smuzhiyun 	.machine_check_exception= mpc7448_machine_check_exception,
190*4882a593Smuzhiyun 	.progress 		= udbg_progress,
191*4882a593Smuzhiyun };
192