1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1997 Geert Uytterhoeven 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is based on the following documentation: 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * The VAS96011/12 Chipset, Data Book, Edition 1.0 9*4882a593Smuzhiyun * VLSI Technology, Inc. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 12*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 13*4882a593Smuzhiyun * for more details. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef _ASMPPC_GG2_H 17*4882a593Smuzhiyun #define _ASMPPC_GG2_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * Memory Map (CHRP mode) 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ 24*4882a593Smuzhiyun #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ 25*4882a593Smuzhiyun #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ 26*4882a593Smuzhiyun #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ 27*4882a593Smuzhiyun #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ 28*4882a593Smuzhiyun /* special PCI cycles */ 29*4882a593Smuzhiyun #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ 30*4882a593Smuzhiyun #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * GG2 specific PCI Registers 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define GG2_PCI_BUSNO 0x40 /* Bus number */ 40*4882a593Smuzhiyun #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ 41*4882a593Smuzhiyun #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ 42*4882a593Smuzhiyun #define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ 43*4882a593Smuzhiyun #define GG2_PCI_ADDR_MAP 0x5c /* Address map */ 44*4882a593Smuzhiyun #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ 45*4882a593Smuzhiyun #define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ 46*4882a593Smuzhiyun #define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ 47*4882a593Smuzhiyun #define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ 48*4882a593Smuzhiyun #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ 49*4882a593Smuzhiyun #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ 50*4882a593Smuzhiyun #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ 51*4882a593Smuzhiyun #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ 52*4882a593Smuzhiyun #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ 53*4882a593Smuzhiyun #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ 54*4882a593Smuzhiyun #define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ 55*4882a593Smuzhiyun #define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ 56*4882a593Smuzhiyun #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ 57*4882a593Smuzhiyun #define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ 58*4882a593Smuzhiyun #define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ 59*4882a593Smuzhiyun /* Cleared when read */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* _ASMPPC_GG2_H */ 62