1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Low-level SPU handling
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Arnd Bergmann <arndb@de.ibm.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #undef DEBUG
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/list.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/ptrace.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <linux/wait.h>
18*4882a593Smuzhiyun #include <linux/mm.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <linux/mutex.h>
21*4882a593Smuzhiyun #include <linux/linux_logo.h>
22*4882a593Smuzhiyun #include <linux/syscore_ops.h>
23*4882a593Smuzhiyun #include <asm/spu.h>
24*4882a593Smuzhiyun #include <asm/spu_priv1.h>
25*4882a593Smuzhiyun #include <asm/spu_csa.h>
26*4882a593Smuzhiyun #include <asm/xmon.h>
27*4882a593Smuzhiyun #include <asm/prom.h>
28*4882a593Smuzhiyun #include <asm/kexec.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun const struct spu_management_ops *spu_management_ops;
31*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_management_ops);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun const struct spu_priv1_ops *spu_priv1_ops;
34*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_priv1_ops);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct cbe_spu_info cbe_spu_info[MAX_NUMNODES];
37*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cbe_spu_info);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * The spufs fault-handling code needs to call force_sig_fault to raise signals
41*4882a593Smuzhiyun * on DMA errors. Export it here to avoid general kernel-wide access to this
42*4882a593Smuzhiyun * function
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(force_sig_fault);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * Protects cbe_spu_info and spu->number.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun static DEFINE_SPINLOCK(spu_lock);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * List of all spus in the system.
53*4882a593Smuzhiyun *
54*4882a593Smuzhiyun * This list is iterated by callers from irq context and callers that
55*4882a593Smuzhiyun * want to sleep. Thus modifications need to be done with both
56*4882a593Smuzhiyun * spu_full_list_lock and spu_full_list_mutex held, while iterating
57*4882a593Smuzhiyun * through it requires either of these locks.
58*4882a593Smuzhiyun *
59*4882a593Smuzhiyun * In addition spu_full_list_lock protects all assignments to
60*4882a593Smuzhiyun * spu->mm.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun static LIST_HEAD(spu_full_list);
63*4882a593Smuzhiyun static DEFINE_SPINLOCK(spu_full_list_lock);
64*4882a593Smuzhiyun static DEFINE_MUTEX(spu_full_list_mutex);
65*4882a593Smuzhiyun
spu_invalidate_slbs(struct spu * spu)66*4882a593Smuzhiyun void spu_invalidate_slbs(struct spu *spu)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct spu_priv2 __iomem *priv2 = spu->priv2;
69*4882a593Smuzhiyun unsigned long flags;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun spin_lock_irqsave(&spu->register_lock, flags);
72*4882a593Smuzhiyun if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
73*4882a593Smuzhiyun out_be64(&priv2->slb_invalidate_all_W, 0UL);
74*4882a593Smuzhiyun spin_unlock_irqrestore(&spu->register_lock, flags);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_invalidate_slbs);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* This is called by the MM core when a segment size is changed, to
79*4882a593Smuzhiyun * request a flush of all the SPEs using a given mm
80*4882a593Smuzhiyun */
spu_flush_all_slbs(struct mm_struct * mm)81*4882a593Smuzhiyun void spu_flush_all_slbs(struct mm_struct *mm)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct spu *spu;
84*4882a593Smuzhiyun unsigned long flags;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun spin_lock_irqsave(&spu_full_list_lock, flags);
87*4882a593Smuzhiyun list_for_each_entry(spu, &spu_full_list, full_list) {
88*4882a593Smuzhiyun if (spu->mm == mm)
89*4882a593Smuzhiyun spu_invalidate_slbs(spu);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun spin_unlock_irqrestore(&spu_full_list_lock, flags);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* The hack below stinks... try to do something better one of
95*4882a593Smuzhiyun * these days... Does it even work properly with NR_CPUS == 1 ?
96*4882a593Smuzhiyun */
mm_needs_global_tlbie(struct mm_struct * mm)97*4882a593Smuzhiyun static inline void mm_needs_global_tlbie(struct mm_struct *mm)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* Global TLBIE broadcast required with SPEs. */
102*4882a593Smuzhiyun bitmap_fill(cpumask_bits(mm_cpumask(mm)), nr);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
spu_associate_mm(struct spu * spu,struct mm_struct * mm)105*4882a593Smuzhiyun void spu_associate_mm(struct spu *spu, struct mm_struct *mm)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun unsigned long flags;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun spin_lock_irqsave(&spu_full_list_lock, flags);
110*4882a593Smuzhiyun spu->mm = mm;
111*4882a593Smuzhiyun spin_unlock_irqrestore(&spu_full_list_lock, flags);
112*4882a593Smuzhiyun if (mm)
113*4882a593Smuzhiyun mm_needs_global_tlbie(mm);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_associate_mm);
116*4882a593Smuzhiyun
spu_64k_pages_available(void)117*4882a593Smuzhiyun int spu_64k_pages_available(void)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun return mmu_psize_defs[MMU_PAGE_64K].shift != 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_64k_pages_available);
122*4882a593Smuzhiyun
spu_restart_dma(struct spu * spu)123*4882a593Smuzhiyun static void spu_restart_dma(struct spu *spu)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct spu_priv2 __iomem *priv2 = spu->priv2;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
128*4882a593Smuzhiyun out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
129*4882a593Smuzhiyun else {
130*4882a593Smuzhiyun set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);
131*4882a593Smuzhiyun mb();
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
spu_load_slb(struct spu * spu,int slbe,struct copro_slb * slb)135*4882a593Smuzhiyun static inline void spu_load_slb(struct spu *spu, int slbe, struct copro_slb *slb)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun struct spu_priv2 __iomem *priv2 = spu->priv2;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun pr_debug("%s: adding SLB[%d] 0x%016llx 0x%016llx\n",
140*4882a593Smuzhiyun __func__, slbe, slb->vsid, slb->esid);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun out_be64(&priv2->slb_index_W, slbe);
143*4882a593Smuzhiyun /* set invalid before writing vsid */
144*4882a593Smuzhiyun out_be64(&priv2->slb_esid_RW, 0);
145*4882a593Smuzhiyun /* now it's safe to write the vsid */
146*4882a593Smuzhiyun out_be64(&priv2->slb_vsid_RW, slb->vsid);
147*4882a593Smuzhiyun /* setting the new esid makes the entry valid again */
148*4882a593Smuzhiyun out_be64(&priv2->slb_esid_RW, slb->esid);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
__spu_trap_data_seg(struct spu * spu,unsigned long ea)151*4882a593Smuzhiyun static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun struct copro_slb slb;
154*4882a593Smuzhiyun int ret;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun ret = copro_calculate_slb(spu->mm, ea, &slb);
157*4882a593Smuzhiyun if (ret)
158*4882a593Smuzhiyun return ret;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun spu_load_slb(spu, spu->slb_replace, &slb);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun spu->slb_replace++;
163*4882a593Smuzhiyun if (spu->slb_replace >= 8)
164*4882a593Smuzhiyun spu->slb_replace = 0;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun spu_restart_dma(spu);
167*4882a593Smuzhiyun spu->stats.slb_flt++;
168*4882a593Smuzhiyun return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun extern int hash_page(unsigned long ea, unsigned long access,
172*4882a593Smuzhiyun unsigned long trap, unsigned long dsisr); //XXX
__spu_trap_data_map(struct spu * spu,unsigned long ea,u64 dsisr)173*4882a593Smuzhiyun static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun int ret;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun * Handle kernel space hash faults immediately. User hash
181*4882a593Smuzhiyun * faults need to be deferred to process context.
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) &&
184*4882a593Smuzhiyun (get_region_id(ea) != USER_REGION_ID)) {
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun spin_unlock(&spu->register_lock);
187*4882a593Smuzhiyun ret = hash_page(ea,
188*4882a593Smuzhiyun _PAGE_PRESENT | _PAGE_READ | _PAGE_PRIVILEGED,
189*4882a593Smuzhiyun 0x300, dsisr);
190*4882a593Smuzhiyun spin_lock(&spu->register_lock);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun if (!ret) {
193*4882a593Smuzhiyun spu_restart_dma(spu);
194*4882a593Smuzhiyun return 0;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun spu->class_1_dar = ea;
199*4882a593Smuzhiyun spu->class_1_dsisr = dsisr;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun spu->stop_callback(spu, 1);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun spu->class_1_dar = 0;
204*4882a593Smuzhiyun spu->class_1_dsisr = 0;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return 0;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
__spu_kernel_slb(void * addr,struct copro_slb * slb)209*4882a593Smuzhiyun static void __spu_kernel_slb(void *addr, struct copro_slb *slb)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun unsigned long ea = (unsigned long)addr;
212*4882a593Smuzhiyun u64 llp;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun if (get_region_id(ea) == LINEAR_MAP_REGION_ID)
215*4882a593Smuzhiyun llp = mmu_psize_defs[mmu_linear_psize].sllp;
216*4882a593Smuzhiyun else
217*4882a593Smuzhiyun llp = mmu_psize_defs[mmu_virtual_psize].sllp;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun slb->vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) << SLB_VSID_SHIFT) |
220*4882a593Smuzhiyun SLB_VSID_KERNEL | llp;
221*4882a593Smuzhiyun slb->esid = (ea & ESID_MASK) | SLB_ESID_V;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /**
225*4882a593Smuzhiyun * Given an array of @nr_slbs SLB entries, @slbs, return non-zero if the
226*4882a593Smuzhiyun * address @new_addr is present.
227*4882a593Smuzhiyun */
__slb_present(struct copro_slb * slbs,int nr_slbs,void * new_addr)228*4882a593Smuzhiyun static inline int __slb_present(struct copro_slb *slbs, int nr_slbs,
229*4882a593Smuzhiyun void *new_addr)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun unsigned long ea = (unsigned long)new_addr;
232*4882a593Smuzhiyun int i;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun for (i = 0; i < nr_slbs; i++)
235*4882a593Smuzhiyun if (!((slbs[i].esid ^ ea) & ESID_MASK))
236*4882a593Smuzhiyun return 1;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun return 0;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /**
242*4882a593Smuzhiyun * Setup the SPU kernel SLBs, in preparation for a context save/restore. We
243*4882a593Smuzhiyun * need to map both the context save area, and the save/restore code.
244*4882a593Smuzhiyun *
245*4882a593Smuzhiyun * Because the lscsa and code may cross segment boundaries, we check to see
246*4882a593Smuzhiyun * if mappings are required for the start and end of each range. We currently
247*4882a593Smuzhiyun * assume that the mappings are smaller that one segment - if not, something
248*4882a593Smuzhiyun * is seriously wrong.
249*4882a593Smuzhiyun */
spu_setup_kernel_slbs(struct spu * spu,struct spu_lscsa * lscsa,void * code,int code_size)250*4882a593Smuzhiyun void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
251*4882a593Smuzhiyun void *code, int code_size)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun struct copro_slb slbs[4];
254*4882a593Smuzhiyun int i, nr_slbs = 0;
255*4882a593Smuzhiyun /* start and end addresses of both mappings */
256*4882a593Smuzhiyun void *addrs[] = {
257*4882a593Smuzhiyun lscsa, (void *)lscsa + sizeof(*lscsa) - 1,
258*4882a593Smuzhiyun code, code + code_size - 1
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* check the set of addresses, and create a new entry in the slbs array
262*4882a593Smuzhiyun * if there isn't already a SLB for that address */
263*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(addrs); i++) {
264*4882a593Smuzhiyun if (__slb_present(slbs, nr_slbs, addrs[i]))
265*4882a593Smuzhiyun continue;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun __spu_kernel_slb(addrs[i], &slbs[nr_slbs]);
268*4882a593Smuzhiyun nr_slbs++;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun spin_lock_irq(&spu->register_lock);
272*4882a593Smuzhiyun /* Add the set of SLBs */
273*4882a593Smuzhiyun for (i = 0; i < nr_slbs; i++)
274*4882a593Smuzhiyun spu_load_slb(spu, i, &slbs[i]);
275*4882a593Smuzhiyun spin_unlock_irq(&spu->register_lock);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static irqreturn_t
spu_irq_class_0(int irq,void * data)280*4882a593Smuzhiyun spu_irq_class_0(int irq, void *data)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun struct spu *spu;
283*4882a593Smuzhiyun unsigned long stat, mask;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun spu = data;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun spin_lock(&spu->register_lock);
288*4882a593Smuzhiyun mask = spu_int_mask_get(spu, 0);
289*4882a593Smuzhiyun stat = spu_int_stat_get(spu, 0) & mask;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun spu->class_0_pending |= stat;
292*4882a593Smuzhiyun spu->class_0_dar = spu_mfc_dar_get(spu);
293*4882a593Smuzhiyun spu->stop_callback(spu, 0);
294*4882a593Smuzhiyun spu->class_0_pending = 0;
295*4882a593Smuzhiyun spu->class_0_dar = 0;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun spu_int_stat_clear(spu, 0, stat);
298*4882a593Smuzhiyun spin_unlock(&spu->register_lock);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun return IRQ_HANDLED;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun static irqreturn_t
spu_irq_class_1(int irq,void * data)304*4882a593Smuzhiyun spu_irq_class_1(int irq, void *data)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun struct spu *spu;
307*4882a593Smuzhiyun unsigned long stat, mask, dar, dsisr;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun spu = data;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* atomically read & clear class1 status. */
312*4882a593Smuzhiyun spin_lock(&spu->register_lock);
313*4882a593Smuzhiyun mask = spu_int_mask_get(spu, 1);
314*4882a593Smuzhiyun stat = spu_int_stat_get(spu, 1) & mask;
315*4882a593Smuzhiyun dar = spu_mfc_dar_get(spu);
316*4882a593Smuzhiyun dsisr = spu_mfc_dsisr_get(spu);
317*4882a593Smuzhiyun if (stat & CLASS1_STORAGE_FAULT_INTR)
318*4882a593Smuzhiyun spu_mfc_dsisr_set(spu, 0ul);
319*4882a593Smuzhiyun spu_int_stat_clear(spu, 1, stat);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,
322*4882a593Smuzhiyun dar, dsisr);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun if (stat & CLASS1_SEGMENT_FAULT_INTR)
325*4882a593Smuzhiyun __spu_trap_data_seg(spu, dar);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun if (stat & CLASS1_STORAGE_FAULT_INTR)
328*4882a593Smuzhiyun __spu_trap_data_map(spu, dar, dsisr);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR)
331*4882a593Smuzhiyun ;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR)
334*4882a593Smuzhiyun ;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun spu->class_1_dsisr = 0;
337*4882a593Smuzhiyun spu->class_1_dar = 0;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun spin_unlock(&spu->register_lock);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun return stat ? IRQ_HANDLED : IRQ_NONE;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static irqreturn_t
spu_irq_class_2(int irq,void * data)345*4882a593Smuzhiyun spu_irq_class_2(int irq, void *data)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun struct spu *spu;
348*4882a593Smuzhiyun unsigned long stat;
349*4882a593Smuzhiyun unsigned long mask;
350*4882a593Smuzhiyun const int mailbox_intrs =
351*4882a593Smuzhiyun CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun spu = data;
354*4882a593Smuzhiyun spin_lock(&spu->register_lock);
355*4882a593Smuzhiyun stat = spu_int_stat_get(spu, 2);
356*4882a593Smuzhiyun mask = spu_int_mask_get(spu, 2);
357*4882a593Smuzhiyun /* ignore interrupts we're not waiting for */
358*4882a593Smuzhiyun stat &= mask;
359*4882a593Smuzhiyun /* mailbox interrupts are level triggered. mask them now before
360*4882a593Smuzhiyun * acknowledging */
361*4882a593Smuzhiyun if (stat & mailbox_intrs)
362*4882a593Smuzhiyun spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));
363*4882a593Smuzhiyun /* acknowledge all interrupts before the callbacks */
364*4882a593Smuzhiyun spu_int_stat_clear(spu, 2, stat);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun if (stat & CLASS2_MAILBOX_INTR)
369*4882a593Smuzhiyun spu->ibox_callback(spu);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (stat & CLASS2_SPU_STOP_INTR)
372*4882a593Smuzhiyun spu->stop_callback(spu, 2);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun if (stat & CLASS2_SPU_HALT_INTR)
375*4882a593Smuzhiyun spu->stop_callback(spu, 2);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR)
378*4882a593Smuzhiyun spu->mfc_callback(spu);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun if (stat & CLASS2_MAILBOX_THRESHOLD_INTR)
381*4882a593Smuzhiyun spu->wbox_callback(spu);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun spu->stats.class2_intr++;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun spin_unlock(&spu->register_lock);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun return stat ? IRQ_HANDLED : IRQ_NONE;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
spu_request_irqs(struct spu * spu)390*4882a593Smuzhiyun static int spu_request_irqs(struct spu *spu)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun int ret = 0;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun if (spu->irqs[0]) {
395*4882a593Smuzhiyun snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",
396*4882a593Smuzhiyun spu->number);
397*4882a593Smuzhiyun ret = request_irq(spu->irqs[0], spu_irq_class_0,
398*4882a593Smuzhiyun 0, spu->irq_c0, spu);
399*4882a593Smuzhiyun if (ret)
400*4882a593Smuzhiyun goto bail0;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun if (spu->irqs[1]) {
403*4882a593Smuzhiyun snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",
404*4882a593Smuzhiyun spu->number);
405*4882a593Smuzhiyun ret = request_irq(spu->irqs[1], spu_irq_class_1,
406*4882a593Smuzhiyun 0, spu->irq_c1, spu);
407*4882a593Smuzhiyun if (ret)
408*4882a593Smuzhiyun goto bail1;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun if (spu->irqs[2]) {
411*4882a593Smuzhiyun snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",
412*4882a593Smuzhiyun spu->number);
413*4882a593Smuzhiyun ret = request_irq(spu->irqs[2], spu_irq_class_2,
414*4882a593Smuzhiyun 0, spu->irq_c2, spu);
415*4882a593Smuzhiyun if (ret)
416*4882a593Smuzhiyun goto bail2;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun return 0;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun bail2:
421*4882a593Smuzhiyun if (spu->irqs[1])
422*4882a593Smuzhiyun free_irq(spu->irqs[1], spu);
423*4882a593Smuzhiyun bail1:
424*4882a593Smuzhiyun if (spu->irqs[0])
425*4882a593Smuzhiyun free_irq(spu->irqs[0], spu);
426*4882a593Smuzhiyun bail0:
427*4882a593Smuzhiyun return ret;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
spu_free_irqs(struct spu * spu)430*4882a593Smuzhiyun static void spu_free_irqs(struct spu *spu)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun if (spu->irqs[0])
433*4882a593Smuzhiyun free_irq(spu->irqs[0], spu);
434*4882a593Smuzhiyun if (spu->irqs[1])
435*4882a593Smuzhiyun free_irq(spu->irqs[1], spu);
436*4882a593Smuzhiyun if (spu->irqs[2])
437*4882a593Smuzhiyun free_irq(spu->irqs[2], spu);
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
spu_init_channels(struct spu * spu)440*4882a593Smuzhiyun void spu_init_channels(struct spu *spu)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun static const struct {
443*4882a593Smuzhiyun unsigned channel;
444*4882a593Smuzhiyun unsigned count;
445*4882a593Smuzhiyun } zero_list[] = {
446*4882a593Smuzhiyun { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
447*4882a593Smuzhiyun { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
448*4882a593Smuzhiyun }, count_list[] = {
449*4882a593Smuzhiyun { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
450*4882a593Smuzhiyun { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
451*4882a593Smuzhiyun { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
452*4882a593Smuzhiyun };
453*4882a593Smuzhiyun struct spu_priv2 __iomem *priv2;
454*4882a593Smuzhiyun int i;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun priv2 = spu->priv2;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun /* initialize all channel data to zero */
459*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
460*4882a593Smuzhiyun int count;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
463*4882a593Smuzhiyun for (count = 0; count < zero_list[i].count; count++)
464*4882a593Smuzhiyun out_be64(&priv2->spu_chnldata_RW, 0);
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun /* initialize channel counts to meaningful values */
468*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(count_list); i++) {
469*4882a593Smuzhiyun out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
470*4882a593Smuzhiyun out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_init_channels);
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun static struct bus_type spu_subsys = {
476*4882a593Smuzhiyun .name = "spu",
477*4882a593Smuzhiyun .dev_name = "spu",
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun
spu_add_dev_attr(struct device_attribute * attr)480*4882a593Smuzhiyun int spu_add_dev_attr(struct device_attribute *attr)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun struct spu *spu;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun mutex_lock(&spu_full_list_mutex);
485*4882a593Smuzhiyun list_for_each_entry(spu, &spu_full_list, full_list)
486*4882a593Smuzhiyun device_create_file(&spu->dev, attr);
487*4882a593Smuzhiyun mutex_unlock(&spu_full_list_mutex);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun return 0;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_add_dev_attr);
492*4882a593Smuzhiyun
spu_add_dev_attr_group(struct attribute_group * attrs)493*4882a593Smuzhiyun int spu_add_dev_attr_group(struct attribute_group *attrs)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun struct spu *spu;
496*4882a593Smuzhiyun int rc = 0;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun mutex_lock(&spu_full_list_mutex);
499*4882a593Smuzhiyun list_for_each_entry(spu, &spu_full_list, full_list) {
500*4882a593Smuzhiyun rc = sysfs_create_group(&spu->dev.kobj, attrs);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun /* we're in trouble here, but try unwinding anyway */
503*4882a593Smuzhiyun if (rc) {
504*4882a593Smuzhiyun printk(KERN_ERR "%s: can't create sysfs group '%s'\n",
505*4882a593Smuzhiyun __func__, attrs->name);
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun list_for_each_entry_continue_reverse(spu,
508*4882a593Smuzhiyun &spu_full_list, full_list)
509*4882a593Smuzhiyun sysfs_remove_group(&spu->dev.kobj, attrs);
510*4882a593Smuzhiyun break;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun mutex_unlock(&spu_full_list_mutex);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun return rc;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_add_dev_attr_group);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun
spu_remove_dev_attr(struct device_attribute * attr)521*4882a593Smuzhiyun void spu_remove_dev_attr(struct device_attribute *attr)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun struct spu *spu;
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun mutex_lock(&spu_full_list_mutex);
526*4882a593Smuzhiyun list_for_each_entry(spu, &spu_full_list, full_list)
527*4882a593Smuzhiyun device_remove_file(&spu->dev, attr);
528*4882a593Smuzhiyun mutex_unlock(&spu_full_list_mutex);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_remove_dev_attr);
531*4882a593Smuzhiyun
spu_remove_dev_attr_group(struct attribute_group * attrs)532*4882a593Smuzhiyun void spu_remove_dev_attr_group(struct attribute_group *attrs)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun struct spu *spu;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun mutex_lock(&spu_full_list_mutex);
537*4882a593Smuzhiyun list_for_each_entry(spu, &spu_full_list, full_list)
538*4882a593Smuzhiyun sysfs_remove_group(&spu->dev.kobj, attrs);
539*4882a593Smuzhiyun mutex_unlock(&spu_full_list_mutex);
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(spu_remove_dev_attr_group);
542*4882a593Smuzhiyun
spu_create_dev(struct spu * spu)543*4882a593Smuzhiyun static int spu_create_dev(struct spu *spu)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun int ret;
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun spu->dev.id = spu->number;
548*4882a593Smuzhiyun spu->dev.bus = &spu_subsys;
549*4882a593Smuzhiyun ret = device_register(&spu->dev);
550*4882a593Smuzhiyun if (ret) {
551*4882a593Smuzhiyun printk(KERN_ERR "Can't register SPU %d with sysfs\n",
552*4882a593Smuzhiyun spu->number);
553*4882a593Smuzhiyun return ret;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun sysfs_add_device_to_node(&spu->dev, spu->node);
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun return 0;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun
create_spu(void * data)561*4882a593Smuzhiyun static int __init create_spu(void *data)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun struct spu *spu;
564*4882a593Smuzhiyun int ret;
565*4882a593Smuzhiyun static int number;
566*4882a593Smuzhiyun unsigned long flags;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun ret = -ENOMEM;
569*4882a593Smuzhiyun spu = kzalloc(sizeof (*spu), GFP_KERNEL);
570*4882a593Smuzhiyun if (!spu)
571*4882a593Smuzhiyun goto out;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun spu->alloc_state = SPU_FREE;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun spin_lock_init(&spu->register_lock);
576*4882a593Smuzhiyun spin_lock(&spu_lock);
577*4882a593Smuzhiyun spu->number = number++;
578*4882a593Smuzhiyun spin_unlock(&spu_lock);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun ret = spu_create_spu(spu, data);
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun if (ret)
583*4882a593Smuzhiyun goto out_free;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun spu_mfc_sdr_setup(spu);
586*4882a593Smuzhiyun spu_mfc_sr1_set(spu, 0x33);
587*4882a593Smuzhiyun ret = spu_request_irqs(spu);
588*4882a593Smuzhiyun if (ret)
589*4882a593Smuzhiyun goto out_destroy;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun ret = spu_create_dev(spu);
592*4882a593Smuzhiyun if (ret)
593*4882a593Smuzhiyun goto out_free_irqs;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun mutex_lock(&cbe_spu_info[spu->node].list_mutex);
596*4882a593Smuzhiyun list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus);
597*4882a593Smuzhiyun cbe_spu_info[spu->node].n_spus++;
598*4882a593Smuzhiyun mutex_unlock(&cbe_spu_info[spu->node].list_mutex);
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun mutex_lock(&spu_full_list_mutex);
601*4882a593Smuzhiyun spin_lock_irqsave(&spu_full_list_lock, flags);
602*4882a593Smuzhiyun list_add(&spu->full_list, &spu_full_list);
603*4882a593Smuzhiyun spin_unlock_irqrestore(&spu_full_list_lock, flags);
604*4882a593Smuzhiyun mutex_unlock(&spu_full_list_mutex);
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun spu->stats.util_state = SPU_UTIL_IDLE_LOADED;
607*4882a593Smuzhiyun spu->stats.tstamp = ktime_get_ns();
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun INIT_LIST_HEAD(&spu->aff_list);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun goto out;
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun out_free_irqs:
614*4882a593Smuzhiyun spu_free_irqs(spu);
615*4882a593Smuzhiyun out_destroy:
616*4882a593Smuzhiyun spu_destroy_spu(spu);
617*4882a593Smuzhiyun out_free:
618*4882a593Smuzhiyun kfree(spu);
619*4882a593Smuzhiyun out:
620*4882a593Smuzhiyun return ret;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun static const char *spu_state_names[] = {
624*4882a593Smuzhiyun "user", "system", "iowait", "idle"
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun
spu_acct_time(struct spu * spu,enum spu_utilization_state state)627*4882a593Smuzhiyun static unsigned long long spu_acct_time(struct spu *spu,
628*4882a593Smuzhiyun enum spu_utilization_state state)
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun unsigned long long time = spu->stats.times[state];
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun /*
633*4882a593Smuzhiyun * If the spu is idle or the context is stopped, utilization
634*4882a593Smuzhiyun * statistics are not updated. Apply the time delta from the
635*4882a593Smuzhiyun * last recorded state of the spu.
636*4882a593Smuzhiyun */
637*4882a593Smuzhiyun if (spu->stats.util_state == state)
638*4882a593Smuzhiyun time += ktime_get_ns() - spu->stats.tstamp;
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun return time / NSEC_PER_MSEC;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun
spu_stat_show(struct device * dev,struct device_attribute * attr,char * buf)644*4882a593Smuzhiyun static ssize_t spu_stat_show(struct device *dev,
645*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
646*4882a593Smuzhiyun {
647*4882a593Smuzhiyun struct spu *spu = container_of(dev, struct spu, dev);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun return sprintf(buf, "%s %llu %llu %llu %llu "
650*4882a593Smuzhiyun "%llu %llu %llu %llu %llu %llu %llu %llu\n",
651*4882a593Smuzhiyun spu_state_names[spu->stats.util_state],
652*4882a593Smuzhiyun spu_acct_time(spu, SPU_UTIL_USER),
653*4882a593Smuzhiyun spu_acct_time(spu, SPU_UTIL_SYSTEM),
654*4882a593Smuzhiyun spu_acct_time(spu, SPU_UTIL_IOWAIT),
655*4882a593Smuzhiyun spu_acct_time(spu, SPU_UTIL_IDLE_LOADED),
656*4882a593Smuzhiyun spu->stats.vol_ctx_switch,
657*4882a593Smuzhiyun spu->stats.invol_ctx_switch,
658*4882a593Smuzhiyun spu->stats.slb_flt,
659*4882a593Smuzhiyun spu->stats.hash_flt,
660*4882a593Smuzhiyun spu->stats.min_flt,
661*4882a593Smuzhiyun spu->stats.maj_flt,
662*4882a593Smuzhiyun spu->stats.class2_intr,
663*4882a593Smuzhiyun spu->stats.libassist);
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL);
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun #ifdef CONFIG_KEXEC_CORE
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun struct crash_spu_info {
671*4882a593Smuzhiyun struct spu *spu;
672*4882a593Smuzhiyun u32 saved_spu_runcntl_RW;
673*4882a593Smuzhiyun u32 saved_spu_status_R;
674*4882a593Smuzhiyun u32 saved_spu_npc_RW;
675*4882a593Smuzhiyun u64 saved_mfc_sr1_RW;
676*4882a593Smuzhiyun u64 saved_mfc_dar;
677*4882a593Smuzhiyun u64 saved_mfc_dsisr;
678*4882a593Smuzhiyun };
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun #define CRASH_NUM_SPUS 16 /* Enough for current hardware */
681*4882a593Smuzhiyun static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS];
682*4882a593Smuzhiyun
crash_kexec_stop_spus(void)683*4882a593Smuzhiyun static void crash_kexec_stop_spus(void)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun struct spu *spu;
686*4882a593Smuzhiyun int i;
687*4882a593Smuzhiyun u64 tmp;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun for (i = 0; i < CRASH_NUM_SPUS; i++) {
690*4882a593Smuzhiyun if (!crash_spu_info[i].spu)
691*4882a593Smuzhiyun continue;
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun spu = crash_spu_info[i].spu;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun crash_spu_info[i].saved_spu_runcntl_RW =
696*4882a593Smuzhiyun in_be32(&spu->problem->spu_runcntl_RW);
697*4882a593Smuzhiyun crash_spu_info[i].saved_spu_status_R =
698*4882a593Smuzhiyun in_be32(&spu->problem->spu_status_R);
699*4882a593Smuzhiyun crash_spu_info[i].saved_spu_npc_RW =
700*4882a593Smuzhiyun in_be32(&spu->problem->spu_npc_RW);
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu);
703*4882a593Smuzhiyun crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu);
704*4882a593Smuzhiyun tmp = spu_mfc_sr1_get(spu);
705*4882a593Smuzhiyun crash_spu_info[i].saved_mfc_sr1_RW = tmp;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
708*4882a593Smuzhiyun spu_mfc_sr1_set(spu, tmp);
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun __delay(200);
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun
crash_register_spus(struct list_head * list)714*4882a593Smuzhiyun static void crash_register_spus(struct list_head *list)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun struct spu *spu;
717*4882a593Smuzhiyun int ret;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun list_for_each_entry(spu, list, full_list) {
720*4882a593Smuzhiyun if (WARN_ON(spu->number >= CRASH_NUM_SPUS))
721*4882a593Smuzhiyun continue;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun crash_spu_info[spu->number].spu = spu;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun ret = crash_shutdown_register(&crash_kexec_stop_spus);
727*4882a593Smuzhiyun if (ret)
728*4882a593Smuzhiyun printk(KERN_ERR "Could not register SPU crash handler");
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun #else
crash_register_spus(struct list_head * list)732*4882a593Smuzhiyun static inline void crash_register_spus(struct list_head *list)
733*4882a593Smuzhiyun {
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun #endif
736*4882a593Smuzhiyun
spu_shutdown(void)737*4882a593Smuzhiyun static void spu_shutdown(void)
738*4882a593Smuzhiyun {
739*4882a593Smuzhiyun struct spu *spu;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun mutex_lock(&spu_full_list_mutex);
742*4882a593Smuzhiyun list_for_each_entry(spu, &spu_full_list, full_list) {
743*4882a593Smuzhiyun spu_free_irqs(spu);
744*4882a593Smuzhiyun spu_destroy_spu(spu);
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun mutex_unlock(&spu_full_list_mutex);
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun static struct syscore_ops spu_syscore_ops = {
750*4882a593Smuzhiyun .shutdown = spu_shutdown,
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun
init_spu_base(void)753*4882a593Smuzhiyun static int __init init_spu_base(void)
754*4882a593Smuzhiyun {
755*4882a593Smuzhiyun int i, ret = 0;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun for (i = 0; i < MAX_NUMNODES; i++) {
758*4882a593Smuzhiyun mutex_init(&cbe_spu_info[i].list_mutex);
759*4882a593Smuzhiyun INIT_LIST_HEAD(&cbe_spu_info[i].spus);
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun if (!spu_management_ops)
763*4882a593Smuzhiyun goto out;
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun /* create system subsystem for spus */
766*4882a593Smuzhiyun ret = subsys_system_register(&spu_subsys, NULL);
767*4882a593Smuzhiyun if (ret)
768*4882a593Smuzhiyun goto out;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun ret = spu_enumerate_spus(create_spu);
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun if (ret < 0) {
773*4882a593Smuzhiyun printk(KERN_WARNING "%s: Error initializing spus\n",
774*4882a593Smuzhiyun __func__);
775*4882a593Smuzhiyun goto out_unregister_subsys;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun if (ret > 0)
779*4882a593Smuzhiyun fb_append_extra_logo(&logo_spe_clut224, ret);
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun mutex_lock(&spu_full_list_mutex);
782*4882a593Smuzhiyun xmon_register_spus(&spu_full_list);
783*4882a593Smuzhiyun crash_register_spus(&spu_full_list);
784*4882a593Smuzhiyun mutex_unlock(&spu_full_list_mutex);
785*4882a593Smuzhiyun spu_add_dev_attr(&dev_attr_stat);
786*4882a593Smuzhiyun register_syscore_ops(&spu_syscore_ops);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun spu_init_affinity();
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun return 0;
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun out_unregister_subsys:
793*4882a593Smuzhiyun bus_unregister(&spu_subsys);
794*4882a593Smuzhiyun out:
795*4882a593Smuzhiyun return ret;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun device_initcall(init_spu_base);
798