1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef ASM_CELL_PIC_H 3*4882a593Smuzhiyun #define ASM_CELL_PIC_H 4*4882a593Smuzhiyun #ifdef __KERNEL__ 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Mapping of IIC pending bits into per-node interrupt numbers. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Interrupt numbers are in the range 0...0x1ff where the top bit 9*4882a593Smuzhiyun * (0x100) represent the source node. Only 2 nodes are supported with 10*4882a593Smuzhiyun * the current code though it's trivial to extend that if necessary using 11*4882a593Smuzhiyun * higher level bits 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The bottom 8 bits are split into 2 type bits and 6 data bits that 14*4882a593Smuzhiyun * depend on the type: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * 00 (0x00 | data) : normal interrupt. data is (class << 4) | source 17*4882a593Smuzhiyun * 01 (0x40 | data) : IO exception. data is the exception number as 18*4882a593Smuzhiyun * defined by bit numbers in IIC_SR 19*4882a593Smuzhiyun * 10 (0x80 | data) : IPI. data is the IPI number (obtained from the priority) 20*4882a593Smuzhiyun * and node is always 0 (IPIs are per-cpu, their source is 21*4882a593Smuzhiyun * not relevant) 22*4882a593Smuzhiyun * 11 (0xc0 | data) : reserved 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * In addition, interrupt number 0x80000000 is defined as always invalid 25*4882a593Smuzhiyun * (that is the node field is expected to never extend to move than 23 bits) 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun enum { 30*4882a593Smuzhiyun IIC_IRQ_INVALID = 0x80000000u, 31*4882a593Smuzhiyun IIC_IRQ_NODE_MASK = 0x100, 32*4882a593Smuzhiyun IIC_IRQ_NODE_SHIFT = 8, 33*4882a593Smuzhiyun IIC_IRQ_MAX = 0x1ff, 34*4882a593Smuzhiyun IIC_IRQ_TYPE_MASK = 0xc0, 35*4882a593Smuzhiyun IIC_IRQ_TYPE_NORMAL = 0x00, 36*4882a593Smuzhiyun IIC_IRQ_TYPE_IOEXC = 0x40, 37*4882a593Smuzhiyun IIC_IRQ_TYPE_IPI = 0x80, 38*4882a593Smuzhiyun IIC_IRQ_CLASS_SHIFT = 4, 39*4882a593Smuzhiyun IIC_IRQ_CLASS_0 = 0x00, 40*4882a593Smuzhiyun IIC_IRQ_CLASS_1 = 0x10, 41*4882a593Smuzhiyun IIC_IRQ_CLASS_2 = 0x20, 42*4882a593Smuzhiyun IIC_SOURCE_COUNT = 0x200, 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Here are defined the various source/dest units. Avoid using those 45*4882a593Smuzhiyun * definitions if you can, they are mostly here for reference 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun IIC_UNIT_SPU_0 = 0x4, 48*4882a593Smuzhiyun IIC_UNIT_SPU_1 = 0x7, 49*4882a593Smuzhiyun IIC_UNIT_SPU_2 = 0x3, 50*4882a593Smuzhiyun IIC_UNIT_SPU_3 = 0x8, 51*4882a593Smuzhiyun IIC_UNIT_SPU_4 = 0x2, 52*4882a593Smuzhiyun IIC_UNIT_SPU_5 = 0x9, 53*4882a593Smuzhiyun IIC_UNIT_SPU_6 = 0x1, 54*4882a593Smuzhiyun IIC_UNIT_SPU_7 = 0xa, 55*4882a593Smuzhiyun IIC_UNIT_IOC_0 = 0x0, 56*4882a593Smuzhiyun IIC_UNIT_IOC_1 = 0xb, 57*4882a593Smuzhiyun IIC_UNIT_THREAD_0 = 0xe, /* target only */ 58*4882a593Smuzhiyun IIC_UNIT_THREAD_1 = 0xf, /* target only */ 59*4882a593Smuzhiyun IIC_UNIT_IIC = 0xe, /* source only (IO exceptions) */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Base numbers for the external interrupts */ 62*4882a593Smuzhiyun IIC_IRQ_EXT_IOIF0 = 63*4882a593Smuzhiyun IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_0, 64*4882a593Smuzhiyun IIC_IRQ_EXT_IOIF1 = 65*4882a593Smuzhiyun IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_1, 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Base numbers for the IIC_ISR interrupts */ 68*4882a593Smuzhiyun IIC_IRQ_IOEX_TMI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 63, 69*4882a593Smuzhiyun IIC_IRQ_IOEX_PMI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 62, 70*4882a593Smuzhiyun IIC_IRQ_IOEX_ATI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 61, 71*4882a593Smuzhiyun IIC_IRQ_IOEX_MATBFI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 60, 72*4882a593Smuzhiyun IIC_IRQ_IOEX_ELDI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 59, 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Which bits in IIC_ISR are edge sensitive */ 75*4882a593Smuzhiyun IIC_ISR_EDGE_MASK = 0x4ul, 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun extern void iic_init_IRQ(void); 79*4882a593Smuzhiyun extern void iic_message_pass(int cpu, int msg); 80*4882a593Smuzhiyun extern void iic_request_IPIs(void); 81*4882a593Smuzhiyun extern void iic_setup_cpu(void); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun extern u8 iic_get_target_id(int cpu); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun extern void spider_init_IRQ(void); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun extern void iic_set_interrupt_routing(int cpu, int thread, int priority); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun #endif /* ASM_CELL_PIC_H */ 91