1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyunconfig PPC_CELL 3*4882a593Smuzhiyun bool 4*4882a593Smuzhiyun 5*4882a593Smuzhiyunconfig PPC_CELL_COMMON 6*4882a593Smuzhiyun bool 7*4882a593Smuzhiyun select PPC_CELL 8*4882a593Smuzhiyun select PPC_DCR_MMIO 9*4882a593Smuzhiyun select PPC_INDIRECT_PIO 10*4882a593Smuzhiyun select PPC_INDIRECT_MMIO 11*4882a593Smuzhiyun select PPC_NATIVE 12*4882a593Smuzhiyun select PPC_RTAS 13*4882a593Smuzhiyun select IRQ_EDGE_EOI_HANDLER 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunconfig PPC_CELL_NATIVE 16*4882a593Smuzhiyun bool 17*4882a593Smuzhiyun select PPC_CELL_COMMON 18*4882a593Smuzhiyun select MPIC 19*4882a593Smuzhiyun select PPC_IO_WORKAROUNDS 20*4882a593Smuzhiyun select IBM_EMAC_EMAC4 if IBM_EMAC 21*4882a593Smuzhiyun select IBM_EMAC_RGMII if IBM_EMAC 22*4882a593Smuzhiyun select IBM_EMAC_ZMII if IBM_EMAC #test only 23*4882a593Smuzhiyun select IBM_EMAC_TAH if IBM_EMAC #test only 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunconfig PPC_IBM_CELL_BLADE 26*4882a593Smuzhiyun bool "IBM Cell Blade" 27*4882a593Smuzhiyun depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN 28*4882a593Smuzhiyun select PPC_CELL_NATIVE 29*4882a593Smuzhiyun select PPC_OF_PLATFORM_PCI 30*4882a593Smuzhiyun select FORCE_PCI 31*4882a593Smuzhiyun select MMIO_NVRAM 32*4882a593Smuzhiyun select PPC_UDBG_16550 33*4882a593Smuzhiyun select UDBG_RTAS_CONSOLE 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig AXON_MSI 36*4882a593Smuzhiyun bool 37*4882a593Smuzhiyun depends on PPC_IBM_CELL_BLADE && PCI_MSI 38*4882a593Smuzhiyun default y 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunmenu "Cell Broadband Engine options" 41*4882a593Smuzhiyun depends on PPC_CELL 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunconfig SPU_FS 44*4882a593Smuzhiyun tristate "SPU file system" 45*4882a593Smuzhiyun default m 46*4882a593Smuzhiyun depends on PPC_CELL 47*4882a593Smuzhiyun depends on COREDUMP 48*4882a593Smuzhiyun select SPU_BASE 49*4882a593Smuzhiyun help 50*4882a593Smuzhiyun The SPU file system is used to access Synergistic Processing 51*4882a593Smuzhiyun Units on machines implementing the Broadband Processor 52*4882a593Smuzhiyun Architecture. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunconfig SPU_BASE 55*4882a593Smuzhiyun bool 56*4882a593Smuzhiyun select PPC_COPRO_BASE 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunconfig CBE_RAS 59*4882a593Smuzhiyun bool "RAS features for bare metal Cell BE" 60*4882a593Smuzhiyun depends on PPC_CELL_NATIVE 61*4882a593Smuzhiyun default y 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunconfig PPC_IBM_CELL_RESETBUTTON 64*4882a593Smuzhiyun bool "IBM Cell Blade Pinhole reset button" 65*4882a593Smuzhiyun depends on CBE_RAS && PPC_IBM_CELL_BLADE 66*4882a593Smuzhiyun default y 67*4882a593Smuzhiyun help 68*4882a593Smuzhiyun Support Pinhole Resetbutton on IBM Cell blades. 69*4882a593Smuzhiyun This adds a method to trigger system reset via front panel pinhole button. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunconfig PPC_IBM_CELL_POWERBUTTON 72*4882a593Smuzhiyun tristate "IBM Cell Blade power button" 73*4882a593Smuzhiyun depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV 74*4882a593Smuzhiyun default y 75*4882a593Smuzhiyun help 76*4882a593Smuzhiyun Support Powerbutton on IBM Cell blades. 77*4882a593Smuzhiyun This will enable the powerbutton as an input device. 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunconfig CBE_THERM 80*4882a593Smuzhiyun tristate "CBE thermal support" 81*4882a593Smuzhiyun default m 82*4882a593Smuzhiyun depends on CBE_RAS && SPU_BASE 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunconfig PPC_PMI 85*4882a593Smuzhiyun tristate 86*4882a593Smuzhiyun default y 87*4882a593Smuzhiyun depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON 88*4882a593Smuzhiyun help 89*4882a593Smuzhiyun PMI (Platform Management Interrupt) is a way to 90*4882a593Smuzhiyun communicate with the BMC (Baseboard Management Controller). 91*4882a593Smuzhiyun It is used in some IBM Cell blades. 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunconfig CBE_CPUFREQ_SPU_GOVERNOR 94*4882a593Smuzhiyun tristate "CBE frequency scaling based on SPU usage" 95*4882a593Smuzhiyun depends on SPU_FS && CPU_FREQ 96*4882a593Smuzhiyun default m 97*4882a593Smuzhiyun help 98*4882a593Smuzhiyun This governor checks for spu usage to adjust the cpu frequency. 99*4882a593Smuzhiyun If no spu is running on a given cpu, that cpu will be throttled to 100*4882a593Smuzhiyun the minimal possible frequency. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunendmenu 103*4882a593Smuzhiyun 104*4882a593Smuzhiyunconfig OPROFILE_CELL 105*4882a593Smuzhiyun def_bool y 106*4882a593Smuzhiyun depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE 107*4882a593Smuzhiyun 108