1*4882a593Smuzhiyun /*arch/powerpc/platforms/8xx/mpc86xads_setup.c
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Platform setup for the Freescale mpc86xads board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Vitaly Bordug <vbordug@ru.mvista.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright 2005 MontaVista Software Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Heavily modified by Scott Wood <scottwood@freescale.com>
10*4882a593Smuzhiyun * Copyright 2007 Freescale Semiconductor, Inc.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
13*4882a593Smuzhiyun * version 2. This program is licensed "as is" without any warranty of any
14*4882a593Smuzhiyun * kind, whether express or implied.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/of_address.h>
19*4882a593Smuzhiyun #include <linux/of_fdt.h>
20*4882a593Smuzhiyun #include <linux/of_platform.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <asm/io.h>
23*4882a593Smuzhiyun #include <asm/machdep.h>
24*4882a593Smuzhiyun #include <asm/time.h>
25*4882a593Smuzhiyun #include <asm/8xx_immap.h>
26*4882a593Smuzhiyun #include <asm/cpm1.h>
27*4882a593Smuzhiyun #include <asm/fs_pd.h>
28*4882a593Smuzhiyun #include <asm/udbg.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "mpc86xads.h"
31*4882a593Smuzhiyun #include "mpc8xx.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct cpm_pin {
34*4882a593Smuzhiyun int port, pin, flags;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static struct cpm_pin mpc866ads_pins[] = {
38*4882a593Smuzhiyun /* SMC1 */
39*4882a593Smuzhiyun {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
40*4882a593Smuzhiyun {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* SMC2 */
43*4882a593Smuzhiyun {CPM_PORTB, 21, CPM_PIN_INPUT}, /* RX */
44*4882a593Smuzhiyun {CPM_PORTB, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* SCC1 */
47*4882a593Smuzhiyun {CPM_PORTA, 6, CPM_PIN_INPUT}, /* CLK1 */
48*4882a593Smuzhiyun {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
49*4882a593Smuzhiyun {CPM_PORTA, 14, CPM_PIN_INPUT}, /* TX */
50*4882a593Smuzhiyun {CPM_PORTA, 15, CPM_PIN_INPUT}, /* RX */
51*4882a593Smuzhiyun {CPM_PORTB, 19, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
52*4882a593Smuzhiyun {CPM_PORTC, 10, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
53*4882a593Smuzhiyun {CPM_PORTC, 11, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* MII */
56*4882a593Smuzhiyun {CPM_PORTD, 3, CPM_PIN_OUTPUT},
57*4882a593Smuzhiyun {CPM_PORTD, 4, CPM_PIN_OUTPUT},
58*4882a593Smuzhiyun {CPM_PORTD, 5, CPM_PIN_OUTPUT},
59*4882a593Smuzhiyun {CPM_PORTD, 6, CPM_PIN_OUTPUT},
60*4882a593Smuzhiyun {CPM_PORTD, 7, CPM_PIN_OUTPUT},
61*4882a593Smuzhiyun {CPM_PORTD, 8, CPM_PIN_OUTPUT},
62*4882a593Smuzhiyun {CPM_PORTD, 9, CPM_PIN_OUTPUT},
63*4882a593Smuzhiyun {CPM_PORTD, 10, CPM_PIN_OUTPUT},
64*4882a593Smuzhiyun {CPM_PORTD, 11, CPM_PIN_OUTPUT},
65*4882a593Smuzhiyun {CPM_PORTD, 12, CPM_PIN_OUTPUT},
66*4882a593Smuzhiyun {CPM_PORTD, 13, CPM_PIN_OUTPUT},
67*4882a593Smuzhiyun {CPM_PORTD, 14, CPM_PIN_OUTPUT},
68*4882a593Smuzhiyun {CPM_PORTD, 15, CPM_PIN_OUTPUT},
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* I2C */
71*4882a593Smuzhiyun {CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
72*4882a593Smuzhiyun {CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
init_ioports(void)75*4882a593Smuzhiyun static void __init init_ioports(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int i;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mpc866ads_pins); i++) {
80*4882a593Smuzhiyun struct cpm_pin *pin = &mpc866ads_pins[i];
81*4882a593Smuzhiyun cpm1_set_pin(pin->port, pin->pin, pin->flags);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
85*4882a593Smuzhiyun cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
86*4882a593Smuzhiyun cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK1, CPM_CLK_TX);
87*4882a593Smuzhiyun cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Set FEC1 and FEC2 to MII mode */
90*4882a593Smuzhiyun clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
mpc86xads_setup_arch(void)93*4882a593Smuzhiyun static void __init mpc86xads_setup_arch(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct device_node *np;
96*4882a593Smuzhiyun u32 __iomem *bcsr_io;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun cpm_reset();
99*4882a593Smuzhiyun init_ioports();
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,mpc866ads-bcsr");
102*4882a593Smuzhiyun if (!np) {
103*4882a593Smuzhiyun printk(KERN_CRIT "Could not find fsl,mpc866ads-bcsr node\n");
104*4882a593Smuzhiyun return;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun bcsr_io = of_iomap(np, 0);
108*4882a593Smuzhiyun of_node_put(np);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (bcsr_io == NULL) {
111*4882a593Smuzhiyun printk(KERN_CRIT "Could not remap BCSR\n");
112*4882a593Smuzhiyun return;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
116*4882a593Smuzhiyun iounmap(bcsr_io);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
mpc86xads_probe(void)119*4882a593Smuzhiyun static int __init mpc86xads_probe(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun return of_machine_is_compatible("fsl,mpc866ads");
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static const struct of_device_id of_bus_ids[] __initconst = {
125*4882a593Smuzhiyun { .name = "soc", },
126*4882a593Smuzhiyun { .name = "cpm", },
127*4882a593Smuzhiyun { .name = "localbus", },
128*4882a593Smuzhiyun {},
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
declare_of_platform_devices(void)131*4882a593Smuzhiyun static int __init declare_of_platform_devices(void)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun of_platform_bus_probe(NULL, of_bus_ids, NULL);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun machine_device_initcall(mpc86x_ads, declare_of_platform_devices);
138*4882a593Smuzhiyun
define_machine(mpc86x_ads)139*4882a593Smuzhiyun define_machine(mpc86x_ads) {
140*4882a593Smuzhiyun .name = "MPC86x ADS",
141*4882a593Smuzhiyun .probe = mpc86xads_probe,
142*4882a593Smuzhiyun .setup_arch = mpc86xads_setup_arch,
143*4882a593Smuzhiyun .init_IRQ = mpc8xx_pics_init,
144*4882a593Smuzhiyun .get_irq = mpc8xx_get_irq,
145*4882a593Smuzhiyun .restart = mpc8xx_restart,
146*4882a593Smuzhiyun .calibrate_decr = mpc8xx_calibrate_decr,
147*4882a593Smuzhiyun .set_rtc_time = mpc8xx_set_rtc_time,
148*4882a593Smuzhiyun .get_rtc_time = mpc8xx_get_rtc_time,
149*4882a593Smuzhiyun .progress = udbg_progress,
150*4882a593Smuzhiyun };
151