1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * A collection of structures, addresses, and values associated with 3*4882a593Smuzhiyun * the Freescale MPC86xADS board. 4*4882a593Smuzhiyun * Copied from the FADS stuff. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: MontaVista Software, Inc. 7*4882a593Smuzhiyun * source@mvista.com 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * 2005 (c) MontaVista Software, Inc. This file is licensed under the 10*4882a593Smuzhiyun * terms of the GNU General Public License version 2. This program is licensed 11*4882a593Smuzhiyun * "as is" without any warranty of any kind, whether express or implied. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifdef __KERNEL__ 15*4882a593Smuzhiyun #ifndef __ASM_MPC86XADS_H__ 16*4882a593Smuzhiyun #define __ASM_MPC86XADS_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Bits of interest in the BCSRs. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define BCSR1_ETHEN ((uint)0x20000000) 21*4882a593Smuzhiyun #define BCSR1_IRDAEN ((uint)0x10000000) 22*4882a593Smuzhiyun #define BCSR1_RS232EN_1 ((uint)0x01000000) 23*4882a593Smuzhiyun #define BCSR1_PCCEN ((uint)0x00800000) 24*4882a593Smuzhiyun #define BCSR1_PCCVCC0 ((uint)0x00400000) 25*4882a593Smuzhiyun #define BCSR1_PCCVPP0 ((uint)0x00200000) 26*4882a593Smuzhiyun #define BCSR1_PCCVPP1 ((uint)0x00100000) 27*4882a593Smuzhiyun #define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1) 28*4882a593Smuzhiyun #define BCSR1_RS232EN_2 ((uint)0x00040000) 29*4882a593Smuzhiyun #define BCSR1_PCCVCC1 ((uint)0x00010000) 30*4882a593Smuzhiyun #define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/ 33*4882a593Smuzhiyun #define BCSR4_USB_LO_SPD ((uint)0x04000000) 34*4882a593Smuzhiyun #define BCSR4_USB_VCC ((uint)0x02000000) 35*4882a593Smuzhiyun #define BCSR4_USB_FULL_SPD ((uint)0x00040000) 36*4882a593Smuzhiyun #define BCSR4_USB_EN ((uint)0x00020000) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define BCSR5_MII2_EN 0x40 39*4882a593Smuzhiyun #define BCSR5_MII2_RST 0x20 40*4882a593Smuzhiyun #define BCSR5_T1_RST 0x10 41*4882a593Smuzhiyun #define BCSR5_ATM155_RST 0x08 42*4882a593Smuzhiyun #define BCSR5_ATM25_RST 0x04 43*4882a593Smuzhiyun #define BCSR5_MII1_EN 0x02 44*4882a593Smuzhiyun #define BCSR5_MII1_RST 0x01 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* __ASM_MPC86XADS_H__ */ 47*4882a593Smuzhiyun #endif /* __KERNEL__ */ 48