1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Author: Xianghua Xiao <x.xiao@freescale.com>
4*4882a593Smuzhiyun * Zhang Wei <wei.zhang@freescale.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2006 Freescale Semiconductor Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/stddef.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/pgtable.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <asm/code-patching.h>
16*4882a593Smuzhiyun #include <asm/page.h>
17*4882a593Smuzhiyun #include <asm/pci-bridge.h>
18*4882a593Smuzhiyun #include <asm/mpic.h>
19*4882a593Smuzhiyun #include <asm/cacheflush.h>
20*4882a593Smuzhiyun #include <asm/inst.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <sysdev/fsl_soc.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "mpc86xx.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun extern void __secondary_start_mpc86xx(void);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define MCM_PORT_CONFIG_OFFSET 0x10
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Offset from CCSRBAR */
31*4882a593Smuzhiyun #define MPC86xx_MCM_OFFSET (0x1000)
32*4882a593Smuzhiyun #define MPC86xx_MCM_SIZE (0x1000)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static void __init
smp_86xx_release_core(int nr)35*4882a593Smuzhiyun smp_86xx_release_core(int nr)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun __be32 __iomem *mcm_vaddr;
38*4882a593Smuzhiyun unsigned long pcr;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if (nr < 0 || nr >= NR_CPUS)
41*4882a593Smuzhiyun return;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * Startup Core #nr.
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
47*4882a593Smuzhiyun MPC86xx_MCM_SIZE);
48*4882a593Smuzhiyun pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2));
49*4882a593Smuzhiyun pcr |= 1 << (nr + 24);
50*4882a593Smuzhiyun out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun iounmap(mcm_vaddr);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static int __init
smp_86xx_kick_cpu(int nr)57*4882a593Smuzhiyun smp_86xx_kick_cpu(int nr)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun unsigned int save_vector;
60*4882a593Smuzhiyun unsigned long target, flags;
61*4882a593Smuzhiyun int n = 0;
62*4882a593Smuzhiyun unsigned int *vector = (unsigned int *)(KERNELBASE + 0x100);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (nr < 0 || nr >= NR_CPUS)
65*4882a593Smuzhiyun return -ENOENT;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun local_irq_save(flags);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Save reset vector */
72*4882a593Smuzhiyun save_vector = *vector;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Setup fake reset vector to call __secondary_start_mpc86xx. */
75*4882a593Smuzhiyun target = (unsigned long) __secondary_start_mpc86xx;
76*4882a593Smuzhiyun patch_branch((struct ppc_inst *)vector, target, BRANCH_SET_LINK);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Kick that CPU */
79*4882a593Smuzhiyun smp_86xx_release_core(nr);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Wait a bit for the CPU to take the exception. */
82*4882a593Smuzhiyun while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000))
83*4882a593Smuzhiyun mdelay(1);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Restore the exception vector */
86*4882a593Smuzhiyun patch_instruction((struct ppc_inst *)vector, ppc_inst(save_vector));
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun local_irq_restore(flags);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun pr_debug("wait CPU #%d for %d msecs.\n", nr, n);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static void __init
smp_86xx_setup_cpu(int cpu_nr)97*4882a593Smuzhiyun smp_86xx_setup_cpu(int cpu_nr)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun mpic_setup_this_cpu();
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun struct smp_ops_t smp_86xx_ops = {
104*4882a593Smuzhiyun .cause_nmi_ipi = NULL,
105*4882a593Smuzhiyun .message_pass = smp_mpic_message_pass,
106*4882a593Smuzhiyun .probe = smp_mpic_probe,
107*4882a593Smuzhiyun .kick_cpu = smp_86xx_kick_cpu,
108*4882a593Smuzhiyun .setup_cpu = smp_86xx_setup_cpu,
109*4882a593Smuzhiyun .take_timebase = smp_generic_take_timebase,
110*4882a593Smuzhiyun .give_timebase = smp_generic_give_timebase,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun void __init
mpc86xx_smp_init(void)115*4882a593Smuzhiyun mpc86xx_smp_init(void)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun smp_ops = &smp_86xx_ops;
118*4882a593Smuzhiyun }
119