xref: /OK3568_Linux_fs/kernel/arch/powerpc/platforms/86xx/gef_sbc310.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * GE SBC310 board support
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Martyn Welch <martyn.welch@ge.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
10*4882a593Smuzhiyun  * Copyright 2006 Freescale Semiconductor Inc.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/stddef.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/kdev_t.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/seq_file.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <asm/time.h>
24*4882a593Smuzhiyun #include <asm/machdep.h>
25*4882a593Smuzhiyun #include <asm/pci-bridge.h>
26*4882a593Smuzhiyun #include <asm/prom.h>
27*4882a593Smuzhiyun #include <mm/mmu_decl.h>
28*4882a593Smuzhiyun #include <asm/udbg.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include <asm/mpic.h>
31*4882a593Smuzhiyun #include <asm/nvram.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include <sysdev/fsl_pci.h>
34*4882a593Smuzhiyun #include <sysdev/fsl_soc.h>
35*4882a593Smuzhiyun #include <sysdev/ge/ge_pic.h>
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #include "mpc86xx.h"
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #undef DEBUG
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #ifdef DEBUG
42*4882a593Smuzhiyun #define DBG (fmt...) do { printk(KERN_ERR "SBC310: " fmt); } while (0)
43*4882a593Smuzhiyun #else
44*4882a593Smuzhiyun #define DBG (fmt...) do { } while (0)
45*4882a593Smuzhiyun #endif
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun void __iomem *sbc310_regs;
48*4882a593Smuzhiyun 
gef_sbc310_init_irq(void)49*4882a593Smuzhiyun static void __init gef_sbc310_init_irq(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	struct device_node *cascade_node = NULL;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	mpc86xx_init_irq();
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	/*
56*4882a593Smuzhiyun 	 * There is a simple interrupt handler in the main FPGA, this needs
57*4882a593Smuzhiyun 	 * to be cascaded into the MPIC
58*4882a593Smuzhiyun 	 */
59*4882a593Smuzhiyun 	cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
60*4882a593Smuzhiyun 	if (!cascade_node) {
61*4882a593Smuzhiyun 		printk(KERN_WARNING "SBC310: No FPGA PIC\n");
62*4882a593Smuzhiyun 		return;
63*4882a593Smuzhiyun 	}
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	gef_pic_init(cascade_node);
66*4882a593Smuzhiyun 	of_node_put(cascade_node);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
gef_sbc310_setup_arch(void)69*4882a593Smuzhiyun static void __init gef_sbc310_setup_arch(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct device_node *regs;
72*4882a593Smuzhiyun 	printk(KERN_INFO "GE Intelligent Platforms SBC310 6U VPX SBC\n");
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #ifdef CONFIG_SMP
75*4882a593Smuzhiyun 	mpc86xx_smp_init();
76*4882a593Smuzhiyun #endif
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	fsl_pci_assign_primary();
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* Remap basic board registers */
81*4882a593Smuzhiyun 	regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
82*4882a593Smuzhiyun 	if (regs) {
83*4882a593Smuzhiyun 		sbc310_regs = of_iomap(regs, 0);
84*4882a593Smuzhiyun 		if (sbc310_regs == NULL)
85*4882a593Smuzhiyun 			printk(KERN_WARNING "Unable to map board registers\n");
86*4882a593Smuzhiyun 		of_node_put(regs);
87*4882a593Smuzhiyun 	}
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #if defined(CONFIG_MMIO_NVRAM)
90*4882a593Smuzhiyun 	mmio_nvram_init();
91*4882a593Smuzhiyun #endif
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /* Return the PCB revision */
gef_sbc310_get_board_id(void)95*4882a593Smuzhiyun static unsigned int gef_sbc310_get_board_id(void)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	unsigned int reg;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	reg = ioread32(sbc310_regs);
100*4882a593Smuzhiyun 	return reg & 0xff;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* Return the PCB revision */
gef_sbc310_get_pcb_rev(void)104*4882a593Smuzhiyun static unsigned int gef_sbc310_get_pcb_rev(void)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	unsigned int reg;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	reg = ioread32(sbc310_regs);
109*4882a593Smuzhiyun 	return (reg >> 8) & 0xff;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* Return the board (software) revision */
gef_sbc310_get_board_rev(void)113*4882a593Smuzhiyun static unsigned int gef_sbc310_get_board_rev(void)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	unsigned int reg;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	reg = ioread32(sbc310_regs);
118*4882a593Smuzhiyun 	return (reg >> 16) & 0xff;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /* Return the FPGA revision */
gef_sbc310_get_fpga_rev(void)122*4882a593Smuzhiyun static unsigned int gef_sbc310_get_fpga_rev(void)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun 	unsigned int reg;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	reg = ioread32(sbc310_regs);
127*4882a593Smuzhiyun 	return (reg >> 24) & 0xf;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
gef_sbc310_show_cpuinfo(struct seq_file * m)130*4882a593Smuzhiyun static void gef_sbc310_show_cpuinfo(struct seq_file *m)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	uint svid = mfspr(SPRN_SVR);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	seq_printf(m, "Board ID\t: 0x%2.2x\n", gef_sbc310_get_board_id());
137*4882a593Smuzhiyun 	seq_printf(m, "Revision\t: %u%c\n", gef_sbc310_get_pcb_rev(),
138*4882a593Smuzhiyun 		('A' + gef_sbc310_get_board_rev() - 1));
139*4882a593Smuzhiyun 	seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc310_get_fpga_rev());
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun 
gef_sbc310_nec_fixup(struct pci_dev * pdev)145*4882a593Smuzhiyun static void gef_sbc310_nec_fixup(struct pci_dev *pdev)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun 	unsigned int val;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* Do not do the fixup on other platforms! */
150*4882a593Smuzhiyun 	if (!machine_is(gef_sbc310))
151*4882a593Smuzhiyun 		return;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	/* Ensure only ports 1 & 2 are enabled */
156*4882a593Smuzhiyun 	pci_read_config_dword(pdev, 0xe0, &val);
157*4882a593Smuzhiyun 	pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x2);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	/* System clock is 48-MHz Oscillator and EHCI Enabled. */
160*4882a593Smuzhiyun 	pci_write_config_dword(pdev, 0xe4, 1 << 5);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
163*4882a593Smuzhiyun 	gef_sbc310_nec_fixup);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun  * Called very early, device-tree isn't unflattened
167*4882a593Smuzhiyun  *
168*4882a593Smuzhiyun  * This function is called to determine whether the BSP is compatible with the
169*4882a593Smuzhiyun  * supplied device-tree, which is assumed to be the correct one for the actual
170*4882a593Smuzhiyun  * board. It is expected thati, in the future, a kernel may support multiple
171*4882a593Smuzhiyun  * boards.
172*4882a593Smuzhiyun  */
gef_sbc310_probe(void)173*4882a593Smuzhiyun static int __init gef_sbc310_probe(void)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	if (of_machine_is_compatible("gef,sbc310"))
176*4882a593Smuzhiyun 		return 1;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	return 0;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun machine_arch_initcall(gef_sbc310, mpc86xx_common_publish_devices);
182*4882a593Smuzhiyun 
define_machine(gef_sbc310)183*4882a593Smuzhiyun define_machine(gef_sbc310) {
184*4882a593Smuzhiyun 	.name			= "GE SBC310",
185*4882a593Smuzhiyun 	.probe			= gef_sbc310_probe,
186*4882a593Smuzhiyun 	.setup_arch		= gef_sbc310_setup_arch,
187*4882a593Smuzhiyun 	.init_IRQ		= gef_sbc310_init_irq,
188*4882a593Smuzhiyun 	.show_cpuinfo		= gef_sbc310_show_cpuinfo,
189*4882a593Smuzhiyun 	.get_irq		= mpic_get_irq,
190*4882a593Smuzhiyun 	.time_init		= mpc86xx_time_init,
191*4882a593Smuzhiyun 	.calibrate_decr		= generic_calibrate_decr,
192*4882a593Smuzhiyun 	.progress		= udbg_progress,
193*4882a593Smuzhiyun #ifdef CONFIG_PCI
194*4882a593Smuzhiyun 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
195*4882a593Smuzhiyun #endif
196*4882a593Smuzhiyun };
197