1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Michael Johnston <michael.johnston@freescale.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Description:
8*4882a593Smuzhiyun * TWR-P102x Board Setup
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/fsl/guts.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/of_platform.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <asm/pci-bridge.h>
19*4882a593Smuzhiyun #include <asm/udbg.h>
20*4882a593Smuzhiyun #include <asm/mpic.h>
21*4882a593Smuzhiyun #include <soc/fsl/qe/qe.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <sysdev/fsl_soc.h>
24*4882a593Smuzhiyun #include <sysdev/fsl_pci.h>
25*4882a593Smuzhiyun #include "smp.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "mpc85xx.h"
28*4882a593Smuzhiyun
twr_p1025_pic_init(void)29*4882a593Smuzhiyun static void __init twr_p1025_pic_init(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct mpic *mpic;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
34*4882a593Smuzhiyun MPIC_SINGLE_DEST_CPU,
35*4882a593Smuzhiyun 0, 256, " OpenPIC ");
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun BUG_ON(mpic == NULL);
38*4882a593Smuzhiyun mpic_init(mpic);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* ************************************************************************
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun * Setup the architecture
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun */
twr_p1025_setup_arch(void)46*4882a593Smuzhiyun static void __init twr_p1025_setup_arch(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun if (ppc_md.progress)
49*4882a593Smuzhiyun ppc_md.progress("twr_p1025_setup_arch()", 0);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun mpc85xx_smp_init();
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun fsl_pci_assign_primary();
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #ifdef CONFIG_QUICC_ENGINE
56*4882a593Smuzhiyun mpc85xx_qe_par_io_init();
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
59*4882a593Smuzhiyun if (machine_is(twr_p1025)) {
60*4882a593Smuzhiyun struct ccsr_guts __iomem *guts;
61*4882a593Smuzhiyun struct device_node *np;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
64*4882a593Smuzhiyun if (np) {
65*4882a593Smuzhiyun guts = of_iomap(np, 0);
66*4882a593Smuzhiyun if (!guts)
67*4882a593Smuzhiyun pr_err("twr_p1025: could not map global utilities register\n");
68*4882a593Smuzhiyun else {
69*4882a593Smuzhiyun /* P1025 has pins muxed for QE and other functions. To
70*4882a593Smuzhiyun * enable QE UEC mode, we need to set bit QE0 for UCC1
71*4882a593Smuzhiyun * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
72*4882a593Smuzhiyun * and QE12 for QE MII management signals in PMUXCR
73*4882a593Smuzhiyun * register.
74*4882a593Smuzhiyun * Set QE mux bits in PMUXCR */
75*4882a593Smuzhiyun setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
76*4882a593Smuzhiyun MPC85xx_PMUXCR_QE(3) |
77*4882a593Smuzhiyun MPC85xx_PMUXCR_QE(9) |
78*4882a593Smuzhiyun MPC85xx_PMUXCR_QE(12));
79*4882a593Smuzhiyun iounmap(guts);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SERIAL_QE)
82*4882a593Smuzhiyun /* On P1025TWR board, the UCC7 acted as UART port.
83*4882a593Smuzhiyun * However, The UCC7's CTS pin is low level in default,
84*4882a593Smuzhiyun * it will impact the transmission in full duplex
85*4882a593Smuzhiyun * communication. So disable the Flow control pin PA18.
86*4882a593Smuzhiyun * The UCC7 UART just can use RXD and TXD pins.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun par_io_config_pin(0, 18, 0, 0, 0, 0);
89*4882a593Smuzhiyun #endif
90*4882a593Smuzhiyun /* Drive PB29 to CPLD low - CPLD will then change
91*4882a593Smuzhiyun * muxing from LBC to QE */
92*4882a593Smuzhiyun par_io_config_pin(1, 29, 1, 0, 0, 0);
93*4882a593Smuzhiyun par_io_data_set(1, 29, 0);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun of_node_put(np);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun #endif
99*4882a593Smuzhiyun #endif /* CONFIG_QUICC_ENGINE */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun pr_info("TWR-P1025 board from Freescale Semiconductor\n");
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
105*4882a593Smuzhiyun
twr_p1025_probe(void)106*4882a593Smuzhiyun static int __init twr_p1025_probe(void)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun return of_machine_is_compatible("fsl,TWR-P1025");
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
define_machine(twr_p1025)111*4882a593Smuzhiyun define_machine(twr_p1025) {
112*4882a593Smuzhiyun .name = "TWR-P1025",
113*4882a593Smuzhiyun .probe = twr_p1025_probe,
114*4882a593Smuzhiyun .setup_arch = twr_p1025_setup_arch,
115*4882a593Smuzhiyun .init_IRQ = twr_p1025_pic_init,
116*4882a593Smuzhiyun #ifdef CONFIG_PCI
117*4882a593Smuzhiyun .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
118*4882a593Smuzhiyun #endif
119*4882a593Smuzhiyun .get_irq = mpic_get_irq,
120*4882a593Smuzhiyun .calibrate_decr = generic_calibrate_decr,
121*4882a593Smuzhiyun .progress = udbg_progress,
122*4882a593Smuzhiyun };
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