1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Based on MPC8560 ADS and arch/ppc tqm85xx ports
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (c) 2005-2006 DENX Software Engineering
10*4882a593Smuzhiyun * Stefan Roese <sr@denx.de>
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Based on original work by
13*4882a593Smuzhiyun * Kumar Gala <kumar.gala@freescale.com>
14*4882a593Smuzhiyun * Copyright 2004 Freescale Semiconductor Inc.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/stddef.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/pci.h>
20*4882a593Smuzhiyun #include <linux/kdev_t.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/seq_file.h>
23*4882a593Smuzhiyun #include <linux/of_platform.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <asm/time.h>
26*4882a593Smuzhiyun #include <asm/machdep.h>
27*4882a593Smuzhiyun #include <asm/pci-bridge.h>
28*4882a593Smuzhiyun #include <asm/mpic.h>
29*4882a593Smuzhiyun #include <asm/prom.h>
30*4882a593Smuzhiyun #include <mm/mmu_decl.h>
31*4882a593Smuzhiyun #include <asm/udbg.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <sysdev/fsl_soc.h>
34*4882a593Smuzhiyun #include <sysdev/fsl_pci.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include "mpc85xx.h"
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #ifdef CONFIG_CPM2
39*4882a593Smuzhiyun #include <asm/cpm2.h>
40*4882a593Smuzhiyun #endif /* CONFIG_CPM2 */
41*4882a593Smuzhiyun
tqm85xx_pic_init(void)42*4882a593Smuzhiyun static void __init tqm85xx_pic_init(void)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct mpic *mpic = mpic_alloc(NULL, 0,
45*4882a593Smuzhiyun MPIC_BIG_ENDIAN,
46*4882a593Smuzhiyun 0, 256, " OpenPIC ");
47*4882a593Smuzhiyun BUG_ON(mpic == NULL);
48*4882a593Smuzhiyun mpic_init(mpic);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun mpc85xx_cpm2_pic_init();
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * Setup the architecture
55*4882a593Smuzhiyun */
tqm85xx_setup_arch(void)56*4882a593Smuzhiyun static void __init tqm85xx_setup_arch(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun if (ppc_md.progress)
59*4882a593Smuzhiyun ppc_md.progress("tqm85xx_setup_arch()", 0);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #ifdef CONFIG_CPM2
62*4882a593Smuzhiyun cpm2_reset();
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun fsl_pci_assign_primary();
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
tqm85xx_show_cpuinfo(struct seq_file * m)68*4882a593Smuzhiyun static void tqm85xx_show_cpuinfo(struct seq_file *m)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun uint pvid, svid, phid1;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun pvid = mfspr(SPRN_PVR);
73*4882a593Smuzhiyun svid = mfspr(SPRN_SVR);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun seq_printf(m, "Vendor\t\t: TQ Components\n");
76*4882a593Smuzhiyun seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
77*4882a593Smuzhiyun seq_printf(m, "SVR\t\t: 0x%x\n", svid);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Display cpu Pll setting */
80*4882a593Smuzhiyun phid1 = mfspr(SPRN_HID1);
81*4882a593Smuzhiyun seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
tqm85xx_ti1520_fixup(struct pci_dev * pdev)84*4882a593Smuzhiyun static void tqm85xx_ti1520_fixup(struct pci_dev *pdev)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun unsigned int val;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Do not do the fixup on other platforms! */
89*4882a593Smuzhiyun if (!machine_is(tqm85xx))
90*4882a593Smuzhiyun return;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun dev_info(&pdev->dev, "Using TI 1520 fixup on TQM85xx\n");
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /*
95*4882a593Smuzhiyun * Enable P2CCLK bit in system control register
96*4882a593Smuzhiyun * to enable CLOCK output to power chip
97*4882a593Smuzhiyun */
98*4882a593Smuzhiyun pci_read_config_dword(pdev, 0x80, &val);
99*4882a593Smuzhiyun pci_write_config_dword(pdev, 0x80, val | (1 << 27));
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
103*4882a593Smuzhiyun tqm85xx_ti1520_fixup);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun machine_arch_initcall(tqm85xx, mpc85xx_common_publish_devices);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const char * const board[] __initconst = {
108*4882a593Smuzhiyun "tqc,tqm8540",
109*4882a593Smuzhiyun "tqc,tqm8541",
110*4882a593Smuzhiyun "tqc,tqm8548",
111*4882a593Smuzhiyun "tqc,tqm8555",
112*4882a593Smuzhiyun "tqc,tqm8560",
113*4882a593Smuzhiyun NULL
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /*
117*4882a593Smuzhiyun * Called very early, device-tree isn't unflattened
118*4882a593Smuzhiyun */
tqm85xx_probe(void)119*4882a593Smuzhiyun static int __init tqm85xx_probe(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun return of_device_compatible_match(of_root, board);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
define_machine(tqm85xx)124*4882a593Smuzhiyun define_machine(tqm85xx) {
125*4882a593Smuzhiyun .name = "TQM85xx",
126*4882a593Smuzhiyun .probe = tqm85xx_probe,
127*4882a593Smuzhiyun .setup_arch = tqm85xx_setup_arch,
128*4882a593Smuzhiyun .init_IRQ = tqm85xx_pic_init,
129*4882a593Smuzhiyun .show_cpuinfo = tqm85xx_show_cpuinfo,
130*4882a593Smuzhiyun .get_irq = mpic_get_irq,
131*4882a593Smuzhiyun .calibrate_decr = generic_calibrate_decr,
132*4882a593Smuzhiyun .progress = udbg_progress,
133*4882a593Smuzhiyun };
134