1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MPC83XX_H__ 3*4882a593Smuzhiyun #define __MPC83XX_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/init.h> 6*4882a593Smuzhiyun #include <linux/device.h> 7*4882a593Smuzhiyun #include <asm/pci-bridge.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* System Clock Control Register */ 10*4882a593Smuzhiyun #define MPC83XX_SCCR_OFFS 0xA08 11*4882a593Smuzhiyun #define MPC83XX_SCCR_USB_MASK 0x00f00000 12*4882a593Smuzhiyun #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000 13*4882a593Smuzhiyun #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000 14*4882a593Smuzhiyun #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000 15*4882a593Smuzhiyun #define MPC83XX_SCCR_USB_DRCM_11 0x00300000 16*4882a593Smuzhiyun #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 17*4882a593Smuzhiyun #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 18*4882a593Smuzhiyun #define MPC8315_SCCR_USB_MASK 0x00c00000 19*4882a593Smuzhiyun #define MPC8315_SCCR_USB_DRCM_11 0x00c00000 20*4882a593Smuzhiyun #define MPC8315_SCCR_USB_DRCM_01 0x00400000 21*4882a593Smuzhiyun #define MPC837X_SCCR_USB_DRCM_11 0x00c00000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* system i/o configuration register low */ 24*4882a593Smuzhiyun #define MPC83XX_SICRL_OFFS 0x114 25*4882a593Smuzhiyun #define MPC834X_SICRL_USB_MASK 0x60000000 26*4882a593Smuzhiyun #define MPC834X_SICRL_USB0 0x20000000 27*4882a593Smuzhiyun #define MPC834X_SICRL_USB1 0x40000000 28*4882a593Smuzhiyun #define MPC831X_SICRL_USB_MASK 0x00000c00 29*4882a593Smuzhiyun #define MPC831X_SICRL_USB_ULPI 0x00000800 30*4882a593Smuzhiyun #define MPC8315_SICRL_USB_MASK 0x000000fc 31*4882a593Smuzhiyun #define MPC8315_SICRL_USB_ULPI 0x00000054 32*4882a593Smuzhiyun #define MPC837X_SICRL_USB_MASK 0xf0000000 33*4882a593Smuzhiyun #define MPC837X_SICRL_USB_ULPI 0x50000000 34*4882a593Smuzhiyun #define MPC837X_SICRL_USBB_MASK 0x30000000 35*4882a593Smuzhiyun #define MPC837X_SICRL_SD 0x20000000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* system i/o configuration register high */ 38*4882a593Smuzhiyun #define MPC83XX_SICRH_OFFS 0x118 39*4882a593Smuzhiyun #define MPC8308_SICRH_USB_MASK 0x000c0000 40*4882a593Smuzhiyun #define MPC8308_SICRH_USB_ULPI 0x00040000 41*4882a593Smuzhiyun #define MPC834X_SICRH_USB_UTMI 0x00020000 42*4882a593Smuzhiyun #define MPC831X_SICRH_USB_MASK 0x000000e0 43*4882a593Smuzhiyun #define MPC831X_SICRH_USB_ULPI 0x000000a0 44*4882a593Smuzhiyun #define MPC8315_SICRH_USB_MASK 0x0000ff00 45*4882a593Smuzhiyun #define MPC8315_SICRH_USB_ULPI 0x00000000 46*4882a593Smuzhiyun #define MPC837X_SICRH_SPI_MASK 0x00000003 47*4882a593Smuzhiyun #define MPC837X_SICRH_SD 0x00000001 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* USB Control Register */ 50*4882a593Smuzhiyun #define FSL_USB2_CONTROL_OFFS 0x500 51*4882a593Smuzhiyun #define CONTROL_UTMI_PHY_EN 0x00000200 52*4882a593Smuzhiyun #define CONTROL_REFSEL_24MHZ 0x00000040 53*4882a593Smuzhiyun #define CONTROL_REFSEL_48MHZ 0x00000080 54*4882a593Smuzhiyun #define CONTROL_PHY_CLK_SEL_ULPI 0x00000400 55*4882a593Smuzhiyun #define CONTROL_OTG_PORT 0x00000020 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* USB PORTSC Registers */ 58*4882a593Smuzhiyun #define FSL_USB2_PORTSC1_OFFS 0x184 59*4882a593Smuzhiyun #define FSL_USB2_PORTSC2_OFFS 0x188 60*4882a593Smuzhiyun #define PORTSCX_PTW_16BIT 0x10000000 61*4882a593Smuzhiyun #define PORTSCX_PTS_UTMI 0x00000000 62*4882a593Smuzhiyun #define PORTSCX_PTS_ULPI 0x80000000 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * Declaration for the various functions exported by the 66*4882a593Smuzhiyun * mpc83xx_* files. Mostly for use by mpc83xx_setup 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun extern void __noreturn mpc83xx_restart(char *cmd); 70*4882a593Smuzhiyun extern long mpc83xx_time_init(void); 71*4882a593Smuzhiyun extern int mpc837x_usb_cfg(void); 72*4882a593Smuzhiyun extern int mpc834x_usb_cfg(void); 73*4882a593Smuzhiyun extern int mpc831x_usb_cfg(void); 74*4882a593Smuzhiyun extern void mpc83xx_ipic_init_IRQ(void); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #ifdef CONFIG_PCI 77*4882a593Smuzhiyun extern void mpc83xx_setup_pci(void); 78*4882a593Smuzhiyun #else 79*4882a593Smuzhiyun #define mpc83xx_setup_pci() do {} while (0) 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun extern int mpc83xx_declare_of_platform_devices(void); 83*4882a593Smuzhiyun extern void mpc83xx_setup_arch(void); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* __MPC83XX_H__ */ 86