1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2008-2011 DENX Software Engineering GmbH
4*4882a593Smuzhiyun * Author: Heiko Schocher <hs@denx.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Description:
7*4882a593Smuzhiyun * Keymile 83xx platform specific routines.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/stddef.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/reboot.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/kdev_t.h>
17*4882a593Smuzhiyun #include <linux/major.h>
18*4882a593Smuzhiyun #include <linux/console.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/seq_file.h>
21*4882a593Smuzhiyun #include <linux/root_dev.h>
22*4882a593Smuzhiyun #include <linux/initrd.h>
23*4882a593Smuzhiyun #include <linux/of_platform.h>
24*4882a593Smuzhiyun #include <linux/of_device.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <linux/atomic.h>
27*4882a593Smuzhiyun #include <linux/time.h>
28*4882a593Smuzhiyun #include <linux/io.h>
29*4882a593Smuzhiyun #include <asm/machdep.h>
30*4882a593Smuzhiyun #include <asm/ipic.h>
31*4882a593Smuzhiyun #include <asm/irq.h>
32*4882a593Smuzhiyun #include <asm/prom.h>
33*4882a593Smuzhiyun #include <asm/udbg.h>
34*4882a593Smuzhiyun #include <sysdev/fsl_soc.h>
35*4882a593Smuzhiyun #include <sysdev/fsl_pci.h>
36*4882a593Smuzhiyun #include <soc/fsl/qe/qe.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include "mpc83xx.h"
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
41*4882a593Smuzhiyun
quirk_mpc8360e_qe_enet10(void)42*4882a593Smuzhiyun static void quirk_mpc8360e_qe_enet10(void)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * handle mpc8360E Erratum QE_ENET10:
46*4882a593Smuzhiyun * RGMII AC values do not meet the specification
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun uint svid = mfspr(SPRN_SVR);
49*4882a593Smuzhiyun struct device_node *np_par;
50*4882a593Smuzhiyun struct resource res;
51*4882a593Smuzhiyun void __iomem *base;
52*4882a593Smuzhiyun int ret;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun np_par = of_find_node_by_name(NULL, "par_io");
55*4882a593Smuzhiyun if (np_par == NULL) {
56*4882a593Smuzhiyun pr_warn("%s couldn't find par_io node\n", __func__);
57*4882a593Smuzhiyun return;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun /* Map Parallel I/O ports registers */
60*4882a593Smuzhiyun ret = of_address_to_resource(np_par, 0, &res);
61*4882a593Smuzhiyun if (ret) {
62*4882a593Smuzhiyun pr_warn("%s couldn't map par_io registers\n", __func__);
63*4882a593Smuzhiyun goto out;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun base = ioremap(res.start, resource_size(&res));
67*4882a593Smuzhiyun if (!base)
68*4882a593Smuzhiyun goto out;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * set output delay adjustments to default values according
72*4882a593Smuzhiyun * table 5 in Errata Rev. 5, 9/2011:
73*4882a593Smuzhiyun *
74*4882a593Smuzhiyun * write 0b01 to UCC1 bits 18:19
75*4882a593Smuzhiyun * write 0b01 to UCC2 option 1 bits 4:5
76*4882a593Smuzhiyun * write 0b01 to UCC2 option 2 bits 16:17
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * set output delay adjustments to default values according
82*4882a593Smuzhiyun * table 3-13 in Reference Manual Rev.3 05/2010:
83*4882a593Smuzhiyun *
84*4882a593Smuzhiyun * write 0b01 to UCC2 option 2 bits 16:17
85*4882a593Smuzhiyun * write 0b0101 to UCC1 bits 20:23
86*4882a593Smuzhiyun * write 0b0101 to UCC2 option 1 bits 24:27
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (SVR_REV(svid) == 0x0021) {
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun * UCC2 option 1: write 0b1010 to bits 24:27
93*4882a593Smuzhiyun * at address IMMRBAR+0x14AC
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
96*4882a593Smuzhiyun } else if (SVR_REV(svid) == 0x0020) {
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * UCC1: write 0b11 to bits 18:19
99*4882a593Smuzhiyun * at address IMMRBAR+0x14A8
100*4882a593Smuzhiyun */
101*4882a593Smuzhiyun setbits32((base + 0xa8), 0x00003000);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun * UCC2 option 1: write 0b11 to bits 4:5
105*4882a593Smuzhiyun * at address IMMRBAR+0x14A8
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun setbits32((base + 0xa8), 0x0c000000);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * UCC2 option 2: write 0b11 to bits 16:17
111*4882a593Smuzhiyun * at address IMMRBAR+0x14AC
112*4882a593Smuzhiyun */
113*4882a593Smuzhiyun setbits32((base + 0xac), 0x0000c000);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun iounmap(base);
116*4882a593Smuzhiyun out:
117*4882a593Smuzhiyun of_node_put(np_par);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* ************************************************************************
121*4882a593Smuzhiyun *
122*4882a593Smuzhiyun * Setup the architecture
123*4882a593Smuzhiyun *
124*4882a593Smuzhiyun */
mpc83xx_km_setup_arch(void)125*4882a593Smuzhiyun static void __init mpc83xx_km_setup_arch(void)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun #ifdef CONFIG_QUICC_ENGINE
128*4882a593Smuzhiyun struct device_node *np;
129*4882a593Smuzhiyun #endif
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun mpc83xx_setup_arch();
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #ifdef CONFIG_QUICC_ENGINE
134*4882a593Smuzhiyun np = of_find_node_by_name(NULL, "par_io");
135*4882a593Smuzhiyun if (np != NULL) {
136*4882a593Smuzhiyun par_io_init(np);
137*4882a593Smuzhiyun of_node_put(np);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun for_each_node_by_name(np, "spi")
140*4882a593Smuzhiyun par_io_of_config(np);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun for_each_node_by_name(np, "ucc")
143*4882a593Smuzhiyun par_io_of_config(np);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* Only apply this quirk when par_io is available */
146*4882a593Smuzhiyun np = of_find_compatible_node(NULL, "network", "ucc_geth");
147*4882a593Smuzhiyun if (np != NULL) {
148*4882a593Smuzhiyun quirk_mpc8360e_qe_enet10();
149*4882a593Smuzhiyun of_node_put(np);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun #endif /* CONFIG_QUICC_ENGINE */
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* list of the supported boards */
158*4882a593Smuzhiyun static char *board[] __initdata = {
159*4882a593Smuzhiyun "Keymile,KMETER1",
160*4882a593Smuzhiyun "Keymile,kmpbec8321",
161*4882a593Smuzhiyun NULL
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun /*
165*4882a593Smuzhiyun * Called very early, MMU is off, device-tree isn't unflattened
166*4882a593Smuzhiyun */
mpc83xx_km_probe(void)167*4882a593Smuzhiyun static int __init mpc83xx_km_probe(void)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun int i = 0;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun while (board[i]) {
172*4882a593Smuzhiyun if (of_machine_is_compatible(board[i]))
173*4882a593Smuzhiyun break;
174*4882a593Smuzhiyun i++;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun return (board[i] != NULL);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
define_machine(mpc83xx_km)179*4882a593Smuzhiyun define_machine(mpc83xx_km) {
180*4882a593Smuzhiyun .name = "mpc83xx-km-platform",
181*4882a593Smuzhiyun .probe = mpc83xx_km_probe,
182*4882a593Smuzhiyun .setup_arch = mpc83xx_km_setup_arch,
183*4882a593Smuzhiyun .init_IRQ = mpc83xx_ipic_init_IRQ,
184*4882a593Smuzhiyun .get_irq = ipic_get_irq,
185*4882a593Smuzhiyun .restart = mpc83xx_restart,
186*4882a593Smuzhiyun .time_init = mpc83xx_time_init,
187*4882a593Smuzhiyun .calibrate_decr = generic_calibrate_decr,
188*4882a593Smuzhiyun .progress = udbg_progress,
189*4882a593Smuzhiyun };
190