1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Common PowerQUICC II code.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Scott Wood <scottwood@freescale.com>
6*4882a593Smuzhiyun * Copyright (c) 2007 Freescale Semiconductor
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
9*4882a593Smuzhiyun * pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
10*4882a593Smuzhiyun * Copyright (c) 2006 MontaVista Software, Inc.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kprobes.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <asm/cpm2.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <asm/pci-bridge.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <platforms/82xx/pq2.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define RMR_CSRE 0x00000001
22*4882a593Smuzhiyun
pq2_restart(char * cmd)23*4882a593Smuzhiyun void __noreturn pq2_restart(char *cmd)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun local_irq_disable();
26*4882a593Smuzhiyun setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
29*4882a593Smuzhiyun mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
30*4882a593Smuzhiyun in_8(&cpm2_immr->im_clkrst.res[0]);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun panic("Restart failed\n");
33*4882a593Smuzhiyun }
NOKPROBE_SYMBOL(pq2_restart)34*4882a593Smuzhiyun NOKPROBE_SYMBOL(pq2_restart)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #ifdef CONFIG_PCI
37*4882a593Smuzhiyun static int pq2_pci_exclude_device(struct pci_controller *hose,
38*4882a593Smuzhiyun u_char bus, u8 devfn)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun if (bus == 0 && PCI_SLOT(devfn) == 0)
41*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
42*4882a593Smuzhiyun else
43*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
pq2_pci_add_bridge(struct device_node * np)46*4882a593Smuzhiyun static void __init pq2_pci_add_bridge(struct device_node *np)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun struct pci_controller *hose;
49*4882a593Smuzhiyun struct resource r;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b)
52*4882a593Smuzhiyun goto err;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun pci_add_flags(PCI_REASSIGN_ALL_BUS);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun hose = pcibios_alloc_controller(np);
57*4882a593Smuzhiyun if (!hose)
58*4882a593Smuzhiyun return;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun hose->dn = np;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0);
63*4882a593Smuzhiyun pci_process_bridge_OF_ranges(hose, np, 1);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun err:
68*4882a593Smuzhiyun printk(KERN_ERR "No valid PCI reg property in device tree\n");
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
pq2_init_pci(void)71*4882a593Smuzhiyun void __init pq2_init_pci(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct device_node *np;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun ppc_md.pci_exclude_device = pq2_pci_exclude_device;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun for_each_compatible_node(np, NULL, "fsl,pq2-pci")
78*4882a593Smuzhiyun pq2_pci_add_bridge(np);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun #endif
81