1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #include <linux/init.h>
3*4882a593Smuzhiyun #include <linux/suspend.h>
4*4882a593Smuzhiyun #include <asm/io.h>
5*4882a593Smuzhiyun #include <asm/time.h>
6*4882a593Smuzhiyun #include <asm/mpc52xx.h>
7*4882a593Smuzhiyun #include <asm/switch_to.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /* defined in lite5200_sleep.S and only used here */
10*4882a593Smuzhiyun extern void lite5200_low_power(void __iomem *sram, void __iomem *mbar);
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun static struct mpc52xx_cdm __iomem *cdm;
13*4882a593Smuzhiyun static struct mpc52xx_intr __iomem *pic;
14*4882a593Smuzhiyun static struct mpc52xx_sdma __iomem *bes;
15*4882a593Smuzhiyun static struct mpc52xx_xlb __iomem *xlb;
16*4882a593Smuzhiyun static struct mpc52xx_gpio __iomem *gps;
17*4882a593Smuzhiyun static struct mpc52xx_gpio_wkup __iomem *gpw;
18*4882a593Smuzhiyun static void __iomem *pci;
19*4882a593Smuzhiyun static void __iomem *sram;
20*4882a593Smuzhiyun static const int sram_size = 0x4000; /* 16 kBytes */
21*4882a593Smuzhiyun static void __iomem *mbar;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static suspend_state_t lite5200_pm_target_state;
24*4882a593Smuzhiyun
lite5200_pm_valid(suspend_state_t state)25*4882a593Smuzhiyun static int lite5200_pm_valid(suspend_state_t state)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun switch (state) {
28*4882a593Smuzhiyun case PM_SUSPEND_STANDBY:
29*4882a593Smuzhiyun case PM_SUSPEND_MEM:
30*4882a593Smuzhiyun return 1;
31*4882a593Smuzhiyun default:
32*4882a593Smuzhiyun return 0;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
lite5200_pm_begin(suspend_state_t state)36*4882a593Smuzhiyun static int lite5200_pm_begin(suspend_state_t state)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun if (lite5200_pm_valid(state)) {
39*4882a593Smuzhiyun lite5200_pm_target_state = state;
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun return -EINVAL;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
lite5200_pm_prepare(void)45*4882a593Smuzhiyun static int lite5200_pm_prepare(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct device_node *np;
48*4882a593Smuzhiyun const struct of_device_id immr_ids[] = {
49*4882a593Smuzhiyun { .compatible = "fsl,mpc5200-immr", },
50*4882a593Smuzhiyun { .compatible = "fsl,mpc5200b-immr", },
51*4882a593Smuzhiyun { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
52*4882a593Smuzhiyun { .type = "builtin", .compatible = "mpc5200", }, /* efika */
53*4882a593Smuzhiyun {}
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun u64 regaddr64 = 0;
56*4882a593Smuzhiyun const u32 *regaddr_p;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* deep sleep? let mpc52xx code handle that */
59*4882a593Smuzhiyun if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
60*4882a593Smuzhiyun return mpc52xx_pm_prepare();
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (lite5200_pm_target_state != PM_SUSPEND_MEM)
63*4882a593Smuzhiyun return -EINVAL;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* map registers */
66*4882a593Smuzhiyun np = of_find_matching_node(NULL, immr_ids);
67*4882a593Smuzhiyun regaddr_p = of_get_address(np, 0, NULL, NULL);
68*4882a593Smuzhiyun if (regaddr_p)
69*4882a593Smuzhiyun regaddr64 = of_translate_address(np, regaddr_p);
70*4882a593Smuzhiyun of_node_put(np);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun mbar = ioremap((u32) regaddr64, 0xC000);
73*4882a593Smuzhiyun if (!mbar) {
74*4882a593Smuzhiyun printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
75*4882a593Smuzhiyun return -ENOSYS;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun cdm = mbar + 0x200;
79*4882a593Smuzhiyun pic = mbar + 0x500;
80*4882a593Smuzhiyun gps = mbar + 0xb00;
81*4882a593Smuzhiyun gpw = mbar + 0xc00;
82*4882a593Smuzhiyun pci = mbar + 0xd00;
83*4882a593Smuzhiyun bes = mbar + 0x1200;
84*4882a593Smuzhiyun xlb = mbar + 0x1f00;
85*4882a593Smuzhiyun sram = mbar + 0x8000;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* save and restore registers not bound to any real devices */
91*4882a593Smuzhiyun static struct mpc52xx_cdm scdm;
92*4882a593Smuzhiyun static struct mpc52xx_intr spic;
93*4882a593Smuzhiyun static struct mpc52xx_sdma sbes;
94*4882a593Smuzhiyun static struct mpc52xx_xlb sxlb;
95*4882a593Smuzhiyun static struct mpc52xx_gpio sgps;
96*4882a593Smuzhiyun static struct mpc52xx_gpio_wkup sgpw;
97*4882a593Smuzhiyun static char spci[0x200];
98*4882a593Smuzhiyun
lite5200_save_regs(void)99*4882a593Smuzhiyun static void lite5200_save_regs(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun _memcpy_fromio(&spic, pic, sizeof(*pic));
102*4882a593Smuzhiyun _memcpy_fromio(&sbes, bes, sizeof(*bes));
103*4882a593Smuzhiyun _memcpy_fromio(&scdm, cdm, sizeof(*cdm));
104*4882a593Smuzhiyun _memcpy_fromio(&sxlb, xlb, sizeof(*xlb));
105*4882a593Smuzhiyun _memcpy_fromio(&sgps, gps, sizeof(*gps));
106*4882a593Smuzhiyun _memcpy_fromio(&sgpw, gpw, sizeof(*gpw));
107*4882a593Smuzhiyun _memcpy_fromio(spci, pci, 0x200);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun _memcpy_fromio(saved_sram, sram, sram_size);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
lite5200_restore_regs(void)112*4882a593Smuzhiyun static void lite5200_restore_regs(void)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun int i;
115*4882a593Smuzhiyun _memcpy_toio(sram, saved_sram, sram_size);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* PCI Configuration */
118*4882a593Smuzhiyun _memcpy_toio(pci, spci, 0x200);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /*
121*4882a593Smuzhiyun * GPIOs. Interrupt Master Enable has higher address then other
122*4882a593Smuzhiyun * registers, so just memcpy is ok.
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun _memcpy_toio(gpw, &sgpw, sizeof(*gpw));
125*4882a593Smuzhiyun _memcpy_toio(gps, &sgps, sizeof(*gps));
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* XLB Arbitrer */
129*4882a593Smuzhiyun out_be32(&xlb->snoop_window, sxlb.snoop_window);
130*4882a593Smuzhiyun out_be32(&xlb->master_priority, sxlb.master_priority);
131*4882a593Smuzhiyun out_be32(&xlb->master_pri_enable, sxlb.master_pri_enable);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* enable */
134*4882a593Smuzhiyun out_be32(&xlb->int_enable, sxlb.int_enable);
135*4882a593Smuzhiyun out_be32(&xlb->config, sxlb.config);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* CDM - Clock Distribution Module */
139*4882a593Smuzhiyun out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel);
140*4882a593Smuzhiyun out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en);
143*4882a593Smuzhiyun out_8(&cdm->fd_enable, scdm.fd_enable);
144*4882a593Smuzhiyun out_be16(&cdm->fd_counters, scdm.fd_counters);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun out_be32(&cdm->clk_enables, scdm.clk_enables);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun out_8(&cdm->osc_disable, scdm.osc_disable);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1);
151*4882a593Smuzhiyun out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2);
152*4882a593Smuzhiyun out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3);
153*4882a593Smuzhiyun out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* BESTCOMM */
157*4882a593Smuzhiyun out_be32(&bes->taskBar, sbes.taskBar);
158*4882a593Smuzhiyun out_be32(&bes->currentPointer, sbes.currentPointer);
159*4882a593Smuzhiyun out_be32(&bes->endPointer, sbes.endPointer);
160*4882a593Smuzhiyun out_be32(&bes->variablePointer, sbes.variablePointer);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun out_8(&bes->IntVect1, sbes.IntVect1);
163*4882a593Smuzhiyun out_8(&bes->IntVect2, sbes.IntVect2);
164*4882a593Smuzhiyun out_be16(&bes->PtdCntrl, sbes.PtdCntrl);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun for (i=0; i<32; i++)
167*4882a593Smuzhiyun out_8(&bes->ipr[i], sbes.ipr[i]);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun out_be32(&bes->cReqSelect, sbes.cReqSelect);
170*4882a593Smuzhiyun out_be32(&bes->task_size0, sbes.task_size0);
171*4882a593Smuzhiyun out_be32(&bes->task_size1, sbes.task_size1);
172*4882a593Smuzhiyun out_be32(&bes->MDEDebug, sbes.MDEDebug);
173*4882a593Smuzhiyun out_be32(&bes->ADSDebug, sbes.ADSDebug);
174*4882a593Smuzhiyun out_be32(&bes->Value1, sbes.Value1);
175*4882a593Smuzhiyun out_be32(&bes->Value2, sbes.Value2);
176*4882a593Smuzhiyun out_be32(&bes->Control, sbes.Control);
177*4882a593Smuzhiyun out_be32(&bes->Status, sbes.Status);
178*4882a593Smuzhiyun out_be32(&bes->PTDDebug, sbes.PTDDebug);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /* restore tasks */
181*4882a593Smuzhiyun for (i=0; i<16; i++)
182*4882a593Smuzhiyun out_be16(&bes->tcr[i], sbes.tcr[i]);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* enable interrupts */
185*4882a593Smuzhiyun out_be32(&bes->IntPend, sbes.IntPend);
186*4882a593Smuzhiyun out_be32(&bes->IntMask, sbes.IntMask);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* PIC */
190*4882a593Smuzhiyun out_be32(&pic->per_pri1, spic.per_pri1);
191*4882a593Smuzhiyun out_be32(&pic->per_pri2, spic.per_pri2);
192*4882a593Smuzhiyun out_be32(&pic->per_pri3, spic.per_pri3);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun out_be32(&pic->main_pri1, spic.main_pri1);
195*4882a593Smuzhiyun out_be32(&pic->main_pri2, spic.main_pri2);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun out_be32(&pic->enc_status, spic.enc_status);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* unmask and enable interrupts */
200*4882a593Smuzhiyun out_be32(&pic->per_mask, spic.per_mask);
201*4882a593Smuzhiyun out_be32(&pic->main_mask, spic.main_mask);
202*4882a593Smuzhiyun out_be32(&pic->ctrl, spic.ctrl);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
lite5200_pm_enter(suspend_state_t state)205*4882a593Smuzhiyun static int lite5200_pm_enter(suspend_state_t state)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun /* deep sleep? let mpc52xx code handle that */
208*4882a593Smuzhiyun if (state == PM_SUSPEND_STANDBY) {
209*4882a593Smuzhiyun return mpc52xx_pm_enter(state);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun lite5200_save_regs();
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* effectively save FP regs */
215*4882a593Smuzhiyun enable_kernel_fp();
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun lite5200_low_power(sram, mbar);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun lite5200_restore_regs();
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun iounmap(mbar);
222*4882a593Smuzhiyun return 0;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
lite5200_pm_finish(void)225*4882a593Smuzhiyun static void lite5200_pm_finish(void)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun /* deep sleep? let mpc52xx code handle that */
228*4882a593Smuzhiyun if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
229*4882a593Smuzhiyun mpc52xx_pm_finish();
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
lite5200_pm_end(void)232*4882a593Smuzhiyun static void lite5200_pm_end(void)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun lite5200_pm_target_state = PM_SUSPEND_ON;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun static const struct platform_suspend_ops lite5200_pm_ops = {
238*4882a593Smuzhiyun .valid = lite5200_pm_valid,
239*4882a593Smuzhiyun .begin = lite5200_pm_begin,
240*4882a593Smuzhiyun .prepare = lite5200_pm_prepare,
241*4882a593Smuzhiyun .enter = lite5200_pm_enter,
242*4882a593Smuzhiyun .finish = lite5200_pm_finish,
243*4882a593Smuzhiyun .end = lite5200_pm_end,
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun
lite5200_pm_init(void)246*4882a593Smuzhiyun int __init lite5200_pm_init(void)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun suspend_set_ops(&lite5200_pm_ops);
249*4882a593Smuzhiyun return 0;
250*4882a593Smuzhiyun }
251