1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * PCI / PCI-X / PCI-Express support for 4xx parts 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Bits and pieces extracted from arch/ppc support by 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Matt Porter <mporter@kernel.crashing.org> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright 2002-2005 MontaVista Software Inc. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef __PPC4XX_PCI_H__ 13*4882a593Smuzhiyun #define __PPC4XX_PCI_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * 4xx PCI-X bridge register definitions 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define PCIX0_VENDID 0x000 19*4882a593Smuzhiyun #define PCIX0_DEVID 0x002 20*4882a593Smuzhiyun #define PCIX0_COMMAND 0x004 21*4882a593Smuzhiyun #define PCIX0_STATUS 0x006 22*4882a593Smuzhiyun #define PCIX0_REVID 0x008 23*4882a593Smuzhiyun #define PCIX0_CLS 0x009 24*4882a593Smuzhiyun #define PCIX0_CACHELS 0x00c 25*4882a593Smuzhiyun #define PCIX0_LATTIM 0x00d 26*4882a593Smuzhiyun #define PCIX0_HDTYPE 0x00e 27*4882a593Smuzhiyun #define PCIX0_BIST 0x00f 28*4882a593Smuzhiyun #define PCIX0_BAR0L 0x010 29*4882a593Smuzhiyun #define PCIX0_BAR0H 0x014 30*4882a593Smuzhiyun #define PCIX0_BAR1 0x018 31*4882a593Smuzhiyun #define PCIX0_BAR2L 0x01c 32*4882a593Smuzhiyun #define PCIX0_BAR2H 0x020 33*4882a593Smuzhiyun #define PCIX0_BAR3 0x024 34*4882a593Smuzhiyun #define PCIX0_CISPTR 0x028 35*4882a593Smuzhiyun #define PCIX0_SBSYSVID 0x02c 36*4882a593Smuzhiyun #define PCIX0_SBSYSID 0x02e 37*4882a593Smuzhiyun #define PCIX0_EROMBA 0x030 38*4882a593Smuzhiyun #define PCIX0_CAP 0x034 39*4882a593Smuzhiyun #define PCIX0_RES0 0x035 40*4882a593Smuzhiyun #define PCIX0_RES1 0x036 41*4882a593Smuzhiyun #define PCIX0_RES2 0x038 42*4882a593Smuzhiyun #define PCIX0_INTLN 0x03c 43*4882a593Smuzhiyun #define PCIX0_INTPN 0x03d 44*4882a593Smuzhiyun #define PCIX0_MINGNT 0x03e 45*4882a593Smuzhiyun #define PCIX0_MAXLTNCY 0x03f 46*4882a593Smuzhiyun #define PCIX0_BRDGOPT1 0x040 47*4882a593Smuzhiyun #define PCIX0_BRDGOPT2 0x044 48*4882a593Smuzhiyun #define PCIX0_ERREN 0x050 49*4882a593Smuzhiyun #define PCIX0_ERRSTS 0x054 50*4882a593Smuzhiyun #define PCIX0_PLBBESR 0x058 51*4882a593Smuzhiyun #define PCIX0_PLBBEARL 0x05c 52*4882a593Smuzhiyun #define PCIX0_PLBBEARH 0x060 53*4882a593Smuzhiyun #define PCIX0_POM0LAL 0x068 54*4882a593Smuzhiyun #define PCIX0_POM0LAH 0x06c 55*4882a593Smuzhiyun #define PCIX0_POM0SA 0x070 56*4882a593Smuzhiyun #define PCIX0_POM0PCIAL 0x074 57*4882a593Smuzhiyun #define PCIX0_POM0PCIAH 0x078 58*4882a593Smuzhiyun #define PCIX0_POM1LAL 0x07c 59*4882a593Smuzhiyun #define PCIX0_POM1LAH 0x080 60*4882a593Smuzhiyun #define PCIX0_POM1SA 0x084 61*4882a593Smuzhiyun #define PCIX0_POM1PCIAL 0x088 62*4882a593Smuzhiyun #define PCIX0_POM1PCIAH 0x08c 63*4882a593Smuzhiyun #define PCIX0_POM2SA 0x090 64*4882a593Smuzhiyun #define PCIX0_PIM0SAL 0x098 65*4882a593Smuzhiyun #define PCIX0_PIM0SA PCIX0_PIM0SAL 66*4882a593Smuzhiyun #define PCIX0_PIM0LAL 0x09c 67*4882a593Smuzhiyun #define PCIX0_PIM0LAH 0x0a0 68*4882a593Smuzhiyun #define PCIX0_PIM1SA 0x0a4 69*4882a593Smuzhiyun #define PCIX0_PIM1LAL 0x0a8 70*4882a593Smuzhiyun #define PCIX0_PIM1LAH 0x0ac 71*4882a593Smuzhiyun #define PCIX0_PIM2SAL 0x0b0 72*4882a593Smuzhiyun #define PCIX0_PIM2SA PCIX0_PIM2SAL 73*4882a593Smuzhiyun #define PCIX0_PIM2LAL 0x0b4 74*4882a593Smuzhiyun #define PCIX0_PIM2LAH 0x0b8 75*4882a593Smuzhiyun #define PCIX0_OMCAPID 0x0c0 76*4882a593Smuzhiyun #define PCIX0_OMNIPTR 0x0c1 77*4882a593Smuzhiyun #define PCIX0_OMMC 0x0c2 78*4882a593Smuzhiyun #define PCIX0_OMMA 0x0c4 79*4882a593Smuzhiyun #define PCIX0_OMMUA 0x0c8 80*4882a593Smuzhiyun #define PCIX0_OMMDATA 0x0cc 81*4882a593Smuzhiyun #define PCIX0_OMMEOI 0x0ce 82*4882a593Smuzhiyun #define PCIX0_PMCAPID 0x0d0 83*4882a593Smuzhiyun #define PCIX0_PMNIPTR 0x0d1 84*4882a593Smuzhiyun #define PCIX0_PMC 0x0d2 85*4882a593Smuzhiyun #define PCIX0_PMCSR 0x0d4 86*4882a593Smuzhiyun #define PCIX0_PMCSRBSE 0x0d6 87*4882a593Smuzhiyun #define PCIX0_PMDATA 0x0d7 88*4882a593Smuzhiyun #define PCIX0_PMSCRR 0x0d8 89*4882a593Smuzhiyun #define PCIX0_CAPID 0x0dc 90*4882a593Smuzhiyun #define PCIX0_NIPTR 0x0dd 91*4882a593Smuzhiyun #define PCIX0_CMD 0x0de 92*4882a593Smuzhiyun #define PCIX0_STS 0x0e0 93*4882a593Smuzhiyun #define PCIX0_IDR 0x0e4 94*4882a593Smuzhiyun #define PCIX0_CID 0x0e8 95*4882a593Smuzhiyun #define PCIX0_RID 0x0ec 96*4882a593Smuzhiyun #define PCIX0_PIM0SAH 0x0f8 97*4882a593Smuzhiyun #define PCIX0_PIM2SAH 0x0fc 98*4882a593Smuzhiyun #define PCIX0_MSGIL 0x100 99*4882a593Smuzhiyun #define PCIX0_MSGIH 0x104 100*4882a593Smuzhiyun #define PCIX0_MSGOL 0x108 101*4882a593Smuzhiyun #define PCIX0_MSGOH 0x10c 102*4882a593Smuzhiyun #define PCIX0_IM 0x1f8 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * 4xx PCI bridge register definitions 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun #define PCIL0_PMM0LA 0x00 108*4882a593Smuzhiyun #define PCIL0_PMM0MA 0x04 109*4882a593Smuzhiyun #define PCIL0_PMM0PCILA 0x08 110*4882a593Smuzhiyun #define PCIL0_PMM0PCIHA 0x0c 111*4882a593Smuzhiyun #define PCIL0_PMM1LA 0x10 112*4882a593Smuzhiyun #define PCIL0_PMM1MA 0x14 113*4882a593Smuzhiyun #define PCIL0_PMM1PCILA 0x18 114*4882a593Smuzhiyun #define PCIL0_PMM1PCIHA 0x1c 115*4882a593Smuzhiyun #define PCIL0_PMM2LA 0x20 116*4882a593Smuzhiyun #define PCIL0_PMM2MA 0x24 117*4882a593Smuzhiyun #define PCIL0_PMM2PCILA 0x28 118*4882a593Smuzhiyun #define PCIL0_PMM2PCIHA 0x2c 119*4882a593Smuzhiyun #define PCIL0_PTM1MS 0x30 120*4882a593Smuzhiyun #define PCIL0_PTM1LA 0x34 121*4882a593Smuzhiyun #define PCIL0_PTM2MS 0x38 122*4882a593Smuzhiyun #define PCIL0_PTM2LA 0x3c 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * 4xx PCIe bridge register definitions 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* DCR offsets */ 129*4882a593Smuzhiyun #define DCRO_PEGPL_CFGBAH 0x00 130*4882a593Smuzhiyun #define DCRO_PEGPL_CFGBAL 0x01 131*4882a593Smuzhiyun #define DCRO_PEGPL_CFGMSK 0x02 132*4882a593Smuzhiyun #define DCRO_PEGPL_MSGBAH 0x03 133*4882a593Smuzhiyun #define DCRO_PEGPL_MSGBAL 0x04 134*4882a593Smuzhiyun #define DCRO_PEGPL_MSGMSK 0x05 135*4882a593Smuzhiyun #define DCRO_PEGPL_OMR1BAH 0x06 136*4882a593Smuzhiyun #define DCRO_PEGPL_OMR1BAL 0x07 137*4882a593Smuzhiyun #define DCRO_PEGPL_OMR1MSKH 0x08 138*4882a593Smuzhiyun #define DCRO_PEGPL_OMR1MSKL 0x09 139*4882a593Smuzhiyun #define DCRO_PEGPL_OMR2BAH 0x0a 140*4882a593Smuzhiyun #define DCRO_PEGPL_OMR2BAL 0x0b 141*4882a593Smuzhiyun #define DCRO_PEGPL_OMR2MSKH 0x0c 142*4882a593Smuzhiyun #define DCRO_PEGPL_OMR2MSKL 0x0d 143*4882a593Smuzhiyun #define DCRO_PEGPL_OMR3BAH 0x0e 144*4882a593Smuzhiyun #define DCRO_PEGPL_OMR3BAL 0x0f 145*4882a593Smuzhiyun #define DCRO_PEGPL_OMR3MSKH 0x10 146*4882a593Smuzhiyun #define DCRO_PEGPL_OMR3MSKL 0x11 147*4882a593Smuzhiyun #define DCRO_PEGPL_REGBAH 0x12 148*4882a593Smuzhiyun #define DCRO_PEGPL_REGBAL 0x13 149*4882a593Smuzhiyun #define DCRO_PEGPL_REGMSK 0x14 150*4882a593Smuzhiyun #define DCRO_PEGPL_SPECIAL 0x15 151*4882a593Smuzhiyun #define DCRO_PEGPL_CFG 0x16 152*4882a593Smuzhiyun #define DCRO_PEGPL_ESR 0x17 153*4882a593Smuzhiyun #define DCRO_PEGPL_EARH 0x18 154*4882a593Smuzhiyun #define DCRO_PEGPL_EARL 0x19 155*4882a593Smuzhiyun #define DCRO_PEGPL_EATR 0x1a 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* DMER mask */ 158*4882a593Smuzhiyun #define GPL_DMER_MASK_DISA 0x02000000 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* 161*4882a593Smuzhiyun * System DCRs (SDRs) 162*4882a593Smuzhiyun */ 163*4882a593Smuzhiyun #define PESDR0_PLLLCT1 0x03a0 164*4882a593Smuzhiyun #define PESDR0_PLLLCT2 0x03a1 165*4882a593Smuzhiyun #define PESDR0_PLLLCT3 0x03a2 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* 168*4882a593Smuzhiyun * 440SPe additional DCRs 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun #define PESDR0_440SPE_UTLSET1 0x0300 171*4882a593Smuzhiyun #define PESDR0_440SPE_UTLSET2 0x0301 172*4882a593Smuzhiyun #define PESDR0_440SPE_DLPSET 0x0302 173*4882a593Smuzhiyun #define PESDR0_440SPE_LOOP 0x0303 174*4882a593Smuzhiyun #define PESDR0_440SPE_RCSSET 0x0304 175*4882a593Smuzhiyun #define PESDR0_440SPE_RCSSTS 0x0305 176*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL0SET1 0x0306 177*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL0SET2 0x0307 178*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL0STS 0x0308 179*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL1SET1 0x0309 180*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL1SET2 0x030a 181*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL1STS 0x030b 182*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL2SET1 0x030c 183*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL2SET2 0x030d 184*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL2STS 0x030e 185*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL3SET1 0x030f 186*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL3SET2 0x0310 187*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL3STS 0x0311 188*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL4SET1 0x0312 189*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL4SET2 0x0313 190*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL4STS 0x0314 191*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL5SET1 0x0315 192*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL5SET2 0x0316 193*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL5STS 0x0317 194*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL6SET1 0x0318 195*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL6SET2 0x0319 196*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL6STS 0x031a 197*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL7SET1 0x031b 198*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL7SET2 0x031c 199*4882a593Smuzhiyun #define PESDR0_440SPE_HSSL7STS 0x031d 200*4882a593Smuzhiyun #define PESDR0_440SPE_HSSCTLSET 0x031e 201*4882a593Smuzhiyun #define PESDR0_440SPE_LANE_ABCD 0x031f 202*4882a593Smuzhiyun #define PESDR0_440SPE_LANE_EFGH 0x0320 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define PESDR1_440SPE_UTLSET1 0x0340 205*4882a593Smuzhiyun #define PESDR1_440SPE_UTLSET2 0x0341 206*4882a593Smuzhiyun #define PESDR1_440SPE_DLPSET 0x0342 207*4882a593Smuzhiyun #define PESDR1_440SPE_LOOP 0x0343 208*4882a593Smuzhiyun #define PESDR1_440SPE_RCSSET 0x0344 209*4882a593Smuzhiyun #define PESDR1_440SPE_RCSSTS 0x0345 210*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL0SET1 0x0346 211*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL0SET2 0x0347 212*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL0STS 0x0348 213*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL1SET1 0x0349 214*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL1SET2 0x034a 215*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL1STS 0x034b 216*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL2SET1 0x034c 217*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL2SET2 0x034d 218*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL2STS 0x034e 219*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL3SET1 0x034f 220*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL3SET2 0x0350 221*4882a593Smuzhiyun #define PESDR1_440SPE_HSSL3STS 0x0351 222*4882a593Smuzhiyun #define PESDR1_440SPE_HSSCTLSET 0x0352 223*4882a593Smuzhiyun #define PESDR1_440SPE_LANE_ABCD 0x0353 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun #define PESDR2_440SPE_UTLSET1 0x0370 226*4882a593Smuzhiyun #define PESDR2_440SPE_UTLSET2 0x0371 227*4882a593Smuzhiyun #define PESDR2_440SPE_DLPSET 0x0372 228*4882a593Smuzhiyun #define PESDR2_440SPE_LOOP 0x0373 229*4882a593Smuzhiyun #define PESDR2_440SPE_RCSSET 0x0374 230*4882a593Smuzhiyun #define PESDR2_440SPE_RCSSTS 0x0375 231*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL0SET1 0x0376 232*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL0SET2 0x0377 233*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL0STS 0x0378 234*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL1SET1 0x0379 235*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL1SET2 0x037a 236*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL1STS 0x037b 237*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL2SET1 0x037c 238*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL2SET2 0x037d 239*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL2STS 0x037e 240*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL3SET1 0x037f 241*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL3SET2 0x0380 242*4882a593Smuzhiyun #define PESDR2_440SPE_HSSL3STS 0x0381 243*4882a593Smuzhiyun #define PESDR2_440SPE_HSSCTLSET 0x0382 244*4882a593Smuzhiyun #define PESDR2_440SPE_LANE_ABCD 0x0383 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* 247*4882a593Smuzhiyun * 405EX additional DCRs 248*4882a593Smuzhiyun */ 249*4882a593Smuzhiyun #define PESDR0_405EX_UTLSET1 0x0400 250*4882a593Smuzhiyun #define PESDR0_405EX_UTLSET2 0x0401 251*4882a593Smuzhiyun #define PESDR0_405EX_DLPSET 0x0402 252*4882a593Smuzhiyun #define PESDR0_405EX_LOOP 0x0403 253*4882a593Smuzhiyun #define PESDR0_405EX_RCSSET 0x0404 254*4882a593Smuzhiyun #define PESDR0_405EX_RCSSTS 0x0405 255*4882a593Smuzhiyun #define PESDR0_405EX_PHYSET1 0x0406 256*4882a593Smuzhiyun #define PESDR0_405EX_PHYSET2 0x0407 257*4882a593Smuzhiyun #define PESDR0_405EX_BIST 0x0408 258*4882a593Smuzhiyun #define PESDR0_405EX_LPB 0x040B 259*4882a593Smuzhiyun #define PESDR0_405EX_PHYSTA 0x040C 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define PESDR1_405EX_UTLSET1 0x0440 262*4882a593Smuzhiyun #define PESDR1_405EX_UTLSET2 0x0441 263*4882a593Smuzhiyun #define PESDR1_405EX_DLPSET 0x0442 264*4882a593Smuzhiyun #define PESDR1_405EX_LOOP 0x0443 265*4882a593Smuzhiyun #define PESDR1_405EX_RCSSET 0x0444 266*4882a593Smuzhiyun #define PESDR1_405EX_RCSSTS 0x0445 267*4882a593Smuzhiyun #define PESDR1_405EX_PHYSET1 0x0446 268*4882a593Smuzhiyun #define PESDR1_405EX_PHYSET2 0x0447 269*4882a593Smuzhiyun #define PESDR1_405EX_BIST 0x0448 270*4882a593Smuzhiyun #define PESDR1_405EX_LPB 0x044B 271*4882a593Smuzhiyun #define PESDR1_405EX_PHYSTA 0x044C 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* 274*4882a593Smuzhiyun * 460EX additional DCRs 275*4882a593Smuzhiyun */ 276*4882a593Smuzhiyun #define PESDR0_460EX_L0BIST 0x0308 277*4882a593Smuzhiyun #define PESDR0_460EX_L0BISTSTS 0x0309 278*4882a593Smuzhiyun #define PESDR0_460EX_L0CDRCTL 0x030A 279*4882a593Smuzhiyun #define PESDR0_460EX_L0DRV 0x030B 280*4882a593Smuzhiyun #define PESDR0_460EX_L0REC 0x030C 281*4882a593Smuzhiyun #define PESDR0_460EX_L0LPB 0x030D 282*4882a593Smuzhiyun #define PESDR0_460EX_L0CLK 0x030E 283*4882a593Smuzhiyun #define PESDR0_460EX_PHY_CTL_RST 0x030F 284*4882a593Smuzhiyun #define PESDR0_460EX_RSTSTA 0x0310 285*4882a593Smuzhiyun #define PESDR0_460EX_OBS 0x0311 286*4882a593Smuzhiyun #define PESDR0_460EX_L0ERRC 0x0320 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define PESDR1_460EX_L0BIST 0x0348 289*4882a593Smuzhiyun #define PESDR1_460EX_L1BIST 0x0349 290*4882a593Smuzhiyun #define PESDR1_460EX_L2BIST 0x034A 291*4882a593Smuzhiyun #define PESDR1_460EX_L3BIST 0x034B 292*4882a593Smuzhiyun #define PESDR1_460EX_L0BISTSTS 0x034C 293*4882a593Smuzhiyun #define PESDR1_460EX_L1BISTSTS 0x034D 294*4882a593Smuzhiyun #define PESDR1_460EX_L2BISTSTS 0x034E 295*4882a593Smuzhiyun #define PESDR1_460EX_L3BISTSTS 0x034F 296*4882a593Smuzhiyun #define PESDR1_460EX_L0CDRCTL 0x0350 297*4882a593Smuzhiyun #define PESDR1_460EX_L1CDRCTL 0x0351 298*4882a593Smuzhiyun #define PESDR1_460EX_L2CDRCTL 0x0352 299*4882a593Smuzhiyun #define PESDR1_460EX_L3CDRCTL 0x0353 300*4882a593Smuzhiyun #define PESDR1_460EX_L0DRV 0x0354 301*4882a593Smuzhiyun #define PESDR1_460EX_L1DRV 0x0355 302*4882a593Smuzhiyun #define PESDR1_460EX_L2DRV 0x0356 303*4882a593Smuzhiyun #define PESDR1_460EX_L3DRV 0x0357 304*4882a593Smuzhiyun #define PESDR1_460EX_L0REC 0x0358 305*4882a593Smuzhiyun #define PESDR1_460EX_L1REC 0x0359 306*4882a593Smuzhiyun #define PESDR1_460EX_L2REC 0x035A 307*4882a593Smuzhiyun #define PESDR1_460EX_L3REC 0x035B 308*4882a593Smuzhiyun #define PESDR1_460EX_L0LPB 0x035C 309*4882a593Smuzhiyun #define PESDR1_460EX_L1LPB 0x035D 310*4882a593Smuzhiyun #define PESDR1_460EX_L2LPB 0x035E 311*4882a593Smuzhiyun #define PESDR1_460EX_L3LPB 0x035F 312*4882a593Smuzhiyun #define PESDR1_460EX_L0CLK 0x0360 313*4882a593Smuzhiyun #define PESDR1_460EX_L1CLK 0x0361 314*4882a593Smuzhiyun #define PESDR1_460EX_L2CLK 0x0362 315*4882a593Smuzhiyun #define PESDR1_460EX_L3CLK 0x0363 316*4882a593Smuzhiyun #define PESDR1_460EX_PHY_CTL_RST 0x0364 317*4882a593Smuzhiyun #define PESDR1_460EX_RSTSTA 0x0365 318*4882a593Smuzhiyun #define PESDR1_460EX_OBS 0x0366 319*4882a593Smuzhiyun #define PESDR1_460EX_L0ERRC 0x0368 320*4882a593Smuzhiyun #define PESDR1_460EX_L1ERRC 0x0369 321*4882a593Smuzhiyun #define PESDR1_460EX_L2ERRC 0x036A 322*4882a593Smuzhiyun #define PESDR1_460EX_L3ERRC 0x036B 323*4882a593Smuzhiyun #define PESDR0_460EX_IHS1 0x036C 324*4882a593Smuzhiyun #define PESDR0_460EX_IHS2 0x036D 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* 327*4882a593Smuzhiyun * 460SX additional DCRs 328*4882a593Smuzhiyun */ 329*4882a593Smuzhiyun #define PESDRn_460SX_RCEI 0x02 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun #define PESDR0_460SX_HSSL0DAMP 0x320 332*4882a593Smuzhiyun #define PESDR0_460SX_HSSL1DAMP 0x321 333*4882a593Smuzhiyun #define PESDR0_460SX_HSSL2DAMP 0x322 334*4882a593Smuzhiyun #define PESDR0_460SX_HSSL3DAMP 0x323 335*4882a593Smuzhiyun #define PESDR0_460SX_HSSL4DAMP 0x324 336*4882a593Smuzhiyun #define PESDR0_460SX_HSSL5DAMP 0x325 337*4882a593Smuzhiyun #define PESDR0_460SX_HSSL6DAMP 0x326 338*4882a593Smuzhiyun #define PESDR0_460SX_HSSL7DAMP 0x327 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun #define PESDR1_460SX_HSSL0DAMP 0x354 341*4882a593Smuzhiyun #define PESDR1_460SX_HSSL1DAMP 0x355 342*4882a593Smuzhiyun #define PESDR1_460SX_HSSL2DAMP 0x356 343*4882a593Smuzhiyun #define PESDR1_460SX_HSSL3DAMP 0x357 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun #define PESDR2_460SX_HSSL0DAMP 0x384 346*4882a593Smuzhiyun #define PESDR2_460SX_HSSL1DAMP 0x385 347*4882a593Smuzhiyun #define PESDR2_460SX_HSSL2DAMP 0x386 348*4882a593Smuzhiyun #define PESDR2_460SX_HSSL3DAMP 0x387 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun #define PESDR0_460SX_HSSL0COEFA 0x328 351*4882a593Smuzhiyun #define PESDR0_460SX_HSSL1COEFA 0x329 352*4882a593Smuzhiyun #define PESDR0_460SX_HSSL2COEFA 0x32A 353*4882a593Smuzhiyun #define PESDR0_460SX_HSSL3COEFA 0x32B 354*4882a593Smuzhiyun #define PESDR0_460SX_HSSL4COEFA 0x32C 355*4882a593Smuzhiyun #define PESDR0_460SX_HSSL5COEFA 0x32D 356*4882a593Smuzhiyun #define PESDR0_460SX_HSSL6COEFA 0x32E 357*4882a593Smuzhiyun #define PESDR0_460SX_HSSL7COEFA 0x32F 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #define PESDR1_460SX_HSSL0COEFA 0x358 360*4882a593Smuzhiyun #define PESDR1_460SX_HSSL1COEFA 0x359 361*4882a593Smuzhiyun #define PESDR1_460SX_HSSL2COEFA 0x35A 362*4882a593Smuzhiyun #define PESDR1_460SX_HSSL3COEFA 0x35B 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun #define PESDR2_460SX_HSSL0COEFA 0x388 365*4882a593Smuzhiyun #define PESDR2_460SX_HSSL1COEFA 0x389 366*4882a593Smuzhiyun #define PESDR2_460SX_HSSL2COEFA 0x38A 367*4882a593Smuzhiyun #define PESDR2_460SX_HSSL3COEFA 0x38B 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #define PESDR0_460SX_HSSL1CALDRV 0x339 370*4882a593Smuzhiyun #define PESDR1_460SX_HSSL1CALDRV 0x361 371*4882a593Smuzhiyun #define PESDR2_460SX_HSSL1CALDRV 0x391 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun #define PESDR0_460SX_HSSSLEW 0x338 374*4882a593Smuzhiyun #define PESDR1_460SX_HSSSLEW 0x360 375*4882a593Smuzhiyun #define PESDR2_460SX_HSSSLEW 0x390 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun #define PESDR0_460SX_HSSCTLSET 0x31E 378*4882a593Smuzhiyun #define PESDR1_460SX_HSSCTLSET 0x352 379*4882a593Smuzhiyun #define PESDR2_460SX_HSSCTLSET 0x382 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun #define PESDR0_460SX_RCSSET 0x304 382*4882a593Smuzhiyun #define PESDR1_460SX_RCSSET 0x344 383*4882a593Smuzhiyun #define PESDR2_460SX_RCSSET 0x374 384*4882a593Smuzhiyun /* 385*4882a593Smuzhiyun * Of the above, some are common offsets from the base 386*4882a593Smuzhiyun */ 387*4882a593Smuzhiyun #define PESDRn_UTLSET1 0x00 388*4882a593Smuzhiyun #define PESDRn_UTLSET2 0x01 389*4882a593Smuzhiyun #define PESDRn_DLPSET 0x02 390*4882a593Smuzhiyun #define PESDRn_LOOP 0x03 391*4882a593Smuzhiyun #define PESDRn_RCSSET 0x04 392*4882a593Smuzhiyun #define PESDRn_RCSSTS 0x05 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun /* 440spe only */ 395*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL0SET1 0x06 396*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL0SET2 0x07 397*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL0STS 0x08 398*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL1SET1 0x09 399*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL1SET2 0x0a 400*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL1STS 0x0b 401*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL2SET1 0x0c 402*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL2SET2 0x0d 403*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL2STS 0x0e 404*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL3SET1 0x0f 405*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL3SET2 0x10 406*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL3STS 0x11 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /* 440spe port 0 only */ 409*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL4SET1 0x12 410*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL4SET2 0x13 411*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL4STS 0x14 412*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL5SET1 0x15 413*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL5SET2 0x16 414*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL5STS 0x17 415*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL6SET1 0x18 416*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL6SET2 0x19 417*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL6STS 0x1a 418*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL7SET1 0x1b 419*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL7SET2 0x1c 420*4882a593Smuzhiyun #define PESDRn_440SPE_HSSL7STS 0x1d 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun /* 405ex only */ 423*4882a593Smuzhiyun #define PESDRn_405EX_PHYSET1 0x06 424*4882a593Smuzhiyun #define PESDRn_405EX_PHYSET2 0x07 425*4882a593Smuzhiyun #define PESDRn_405EX_PHYSTA 0x0c 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun /* 428*4882a593Smuzhiyun * UTL register offsets 429*4882a593Smuzhiyun */ 430*4882a593Smuzhiyun #define PEUTL_PBCTL 0x00 431*4882a593Smuzhiyun #define PEUTL_PBBSZ 0x20 432*4882a593Smuzhiyun #define PEUTL_OPDBSZ 0x68 433*4882a593Smuzhiyun #define PEUTL_IPHBSZ 0x70 434*4882a593Smuzhiyun #define PEUTL_IPDBSZ 0x78 435*4882a593Smuzhiyun #define PEUTL_OUTTR 0x90 436*4882a593Smuzhiyun #define PEUTL_INTR 0x98 437*4882a593Smuzhiyun #define PEUTL_PCTL 0xa0 438*4882a593Smuzhiyun #define PEUTL_RCSTA 0xB0 439*4882a593Smuzhiyun #define PEUTL_RCIRQEN 0xb8 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun /* 442*4882a593Smuzhiyun * Config space register offsets 443*4882a593Smuzhiyun */ 444*4882a593Smuzhiyun #define PECFG_ECRTCTL 0x074 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun #define PECFG_BAR0LMPA 0x210 447*4882a593Smuzhiyun #define PECFG_BAR0HMPA 0x214 448*4882a593Smuzhiyun #define PECFG_BAR1MPA 0x218 449*4882a593Smuzhiyun #define PECFG_BAR2LMPA 0x220 450*4882a593Smuzhiyun #define PECFG_BAR2HMPA 0x224 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun #define PECFG_PIMEN 0x33c 453*4882a593Smuzhiyun #define PECFG_PIM0LAL 0x340 454*4882a593Smuzhiyun #define PECFG_PIM0LAH 0x344 455*4882a593Smuzhiyun #define PECFG_PIM1LAL 0x348 456*4882a593Smuzhiyun #define PECFG_PIM1LAH 0x34c 457*4882a593Smuzhiyun #define PECFG_PIM01SAL 0x350 458*4882a593Smuzhiyun #define PECFG_PIM01SAH 0x354 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun #define PECFG_POM0LAL 0x380 461*4882a593Smuzhiyun #define PECFG_POM0LAH 0x384 462*4882a593Smuzhiyun #define PECFG_POM1LAL 0x388 463*4882a593Smuzhiyun #define PECFG_POM1LAH 0x38c 464*4882a593Smuzhiyun #define PECFG_POM2LAL 0x390 465*4882a593Smuzhiyun #define PECFG_POM2LAH 0x394 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun /* 460sx only */ 468*4882a593Smuzhiyun #define PECFG_460SX_DLLSTA 0x3f8 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun /* 460sx Bit Mappings */ 471*4882a593Smuzhiyun #define PECFG_460SX_DLLSTA_LINKUP 0x00000010 472*4882a593Smuzhiyun #define DCRO_PEGPL_460SX_OMR1MSKL_UOT 0x00000004 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun /* PEGPL Bit Mappings */ 475*4882a593Smuzhiyun #define DCRO_PEGPL_OMRxMSKL_VAL 0x00000001 476*4882a593Smuzhiyun #define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002 477*4882a593Smuzhiyun #define DCRO_PEGPL_OMR3MSKL_IO 0x00000002 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun /* 476FPE */ 480*4882a593Smuzhiyun #define PCCFG_LCPA 0x270 481*4882a593Smuzhiyun #define PECFG_TLDLP 0x3F8 482*4882a593Smuzhiyun #define PECFG_TLDLP_LNKUP 0x00000008 483*4882a593Smuzhiyun #define PECFG_TLDLP_PRESENT 0x00000010 484*4882a593Smuzhiyun #define DCRO_PEGPL_476FPE_OMR1MSKL_UOT 0x00000004 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun /* SDR Bit Mappings */ 487*4882a593Smuzhiyun #define PESDRx_RCSSET_HLDPLB 0x10000000 488*4882a593Smuzhiyun #define PESDRx_RCSSET_RSTGU 0x01000000 489*4882a593Smuzhiyun #define PESDRx_RCSSET_RDY 0x00100000 490*4882a593Smuzhiyun #define PESDRx_RCSSET_RSTDL 0x00010000 491*4882a593Smuzhiyun #define PESDRx_RCSSET_RSTPYN 0x00001000 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun enum 494*4882a593Smuzhiyun { 495*4882a593Smuzhiyun PTYPE_ENDPOINT = 0x0, 496*4882a593Smuzhiyun PTYPE_LEGACY_ENDPOINT = 0x1, 497*4882a593Smuzhiyun PTYPE_ROOT_PORT = 0x4, 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun LNKW_X1 = 0x1, 500*4882a593Smuzhiyun LNKW_X4 = 0x4, 501*4882a593Smuzhiyun LNKW_X8 = 0x8 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun #endif /* __PPC4XX_PCI_H__ */ 506