1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MSI support for PPC4xx SoCs using High Speed Transfer Assist (HSTA) for
4*4882a593Smuzhiyun * generation of the interrupt.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright © 2013 Alistair Popple <alistair@popple.id.au> IBM Corporation
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/msi.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/semaphore.h>
16*4882a593Smuzhiyun #include <asm/msi_bitmap.h>
17*4882a593Smuzhiyun #include <asm/ppc-pci.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct ppc4xx_hsta_msi {
20*4882a593Smuzhiyun struct device *dev;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* The ioremapped HSTA MSI IO space */
23*4882a593Smuzhiyun u32 __iomem *data;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Physical address of HSTA MSI IO space */
26*4882a593Smuzhiyun u64 address;
27*4882a593Smuzhiyun struct msi_bitmap bmp;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* An array mapping offsets to hardware IRQs */
30*4882a593Smuzhiyun int *irq_map;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Number of hwirqs supported */
33*4882a593Smuzhiyun int irq_count;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun static struct ppc4xx_hsta_msi ppc4xx_hsta_msi;
36*4882a593Smuzhiyun
hsta_setup_msi_irqs(struct pci_dev * dev,int nvec,int type)37*4882a593Smuzhiyun static int hsta_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct msi_msg msg;
40*4882a593Smuzhiyun struct msi_desc *entry;
41*4882a593Smuzhiyun int irq, hwirq;
42*4882a593Smuzhiyun u64 addr;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* We don't support MSI-X */
45*4882a593Smuzhiyun if (type == PCI_CAP_ID_MSIX) {
46*4882a593Smuzhiyun pr_debug("%s: MSI-X not supported.\n", __func__);
47*4882a593Smuzhiyun return -EINVAL;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun for_each_pci_msi_entry(entry, dev) {
51*4882a593Smuzhiyun irq = msi_bitmap_alloc_hwirqs(&ppc4xx_hsta_msi.bmp, 1);
52*4882a593Smuzhiyun if (irq < 0) {
53*4882a593Smuzhiyun pr_debug("%s: Failed to allocate msi interrupt\n",
54*4882a593Smuzhiyun __func__);
55*4882a593Smuzhiyun return irq;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun hwirq = ppc4xx_hsta_msi.irq_map[irq];
59*4882a593Smuzhiyun if (!hwirq) {
60*4882a593Smuzhiyun pr_err("%s: Failed mapping irq %d\n", __func__, irq);
61*4882a593Smuzhiyun return -EINVAL;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * HSTA generates interrupts on writes to 128-bit aligned
66*4882a593Smuzhiyun * addresses.
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun addr = ppc4xx_hsta_msi.address + irq*0x10;
69*4882a593Smuzhiyun msg.address_hi = upper_32_bits(addr);
70*4882a593Smuzhiyun msg.address_lo = lower_32_bits(addr);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Data is not used by the HSTA. */
73*4882a593Smuzhiyun msg.data = 0;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun pr_debug("%s: Setup irq %d (0x%0llx)\n", __func__, hwirq,
76*4882a593Smuzhiyun (((u64) msg.address_hi) << 32) | msg.address_lo);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (irq_set_msi_desc(hwirq, entry)) {
79*4882a593Smuzhiyun pr_err(
80*4882a593Smuzhiyun "%s: Invalid hwirq %d specified in device tree\n",
81*4882a593Smuzhiyun __func__, hwirq);
82*4882a593Smuzhiyun msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
83*4882a593Smuzhiyun return -EINVAL;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun pci_write_msi_msg(hwirq, &msg);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
hsta_find_hwirq_offset(int hwirq)91*4882a593Smuzhiyun static int hsta_find_hwirq_offset(int hwirq)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int irq;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Find the offset given the hwirq */
96*4882a593Smuzhiyun for (irq = 0; irq < ppc4xx_hsta_msi.irq_count; irq++)
97*4882a593Smuzhiyun if (ppc4xx_hsta_msi.irq_map[irq] == hwirq)
98*4882a593Smuzhiyun return irq;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return -EINVAL;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
hsta_teardown_msi_irqs(struct pci_dev * dev)103*4882a593Smuzhiyun static void hsta_teardown_msi_irqs(struct pci_dev *dev)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct msi_desc *entry;
106*4882a593Smuzhiyun int irq;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun for_each_pci_msi_entry(entry, dev) {
109*4882a593Smuzhiyun if (!entry->irq)
110*4882a593Smuzhiyun continue;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun irq = hsta_find_hwirq_offset(entry->irq);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* entry->irq should always be in irq_map */
115*4882a593Smuzhiyun BUG_ON(irq < 0);
116*4882a593Smuzhiyun irq_set_msi_desc(entry->irq, NULL);
117*4882a593Smuzhiyun msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
118*4882a593Smuzhiyun pr_debug("%s: Teardown IRQ %u (index %u)\n", __func__,
119*4882a593Smuzhiyun entry->irq, irq);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
hsta_msi_probe(struct platform_device * pdev)123*4882a593Smuzhiyun static int hsta_msi_probe(struct platform_device *pdev)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct device *dev = &pdev->dev;
126*4882a593Smuzhiyun struct resource *mem;
127*4882a593Smuzhiyun int irq, ret, irq_count;
128*4882a593Smuzhiyun struct pci_controller *phb;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
131*4882a593Smuzhiyun if (!mem) {
132*4882a593Smuzhiyun dev_err(dev, "Unable to get mmio space\n");
133*4882a593Smuzhiyun return -EINVAL;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun irq_count = of_irq_count(dev->of_node);
137*4882a593Smuzhiyun if (!irq_count) {
138*4882a593Smuzhiyun dev_err(dev, "Unable to find IRQ range\n");
139*4882a593Smuzhiyun return -EINVAL;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun ppc4xx_hsta_msi.dev = dev;
143*4882a593Smuzhiyun ppc4xx_hsta_msi.address = mem->start;
144*4882a593Smuzhiyun ppc4xx_hsta_msi.data = ioremap(mem->start, resource_size(mem));
145*4882a593Smuzhiyun ppc4xx_hsta_msi.irq_count = irq_count;
146*4882a593Smuzhiyun if (!ppc4xx_hsta_msi.data) {
147*4882a593Smuzhiyun dev_err(dev, "Unable to map memory\n");
148*4882a593Smuzhiyun return -ENOMEM;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun ret = msi_bitmap_alloc(&ppc4xx_hsta_msi.bmp, irq_count, dev->of_node);
152*4882a593Smuzhiyun if (ret)
153*4882a593Smuzhiyun goto out;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun ppc4xx_hsta_msi.irq_map = kmalloc_array(irq_count, sizeof(int),
156*4882a593Smuzhiyun GFP_KERNEL);
157*4882a593Smuzhiyun if (!ppc4xx_hsta_msi.irq_map) {
158*4882a593Smuzhiyun ret = -ENOMEM;
159*4882a593Smuzhiyun goto out1;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* Setup a mapping from irq offsets to hardware irq numbers */
163*4882a593Smuzhiyun for (irq = 0; irq < irq_count; irq++) {
164*4882a593Smuzhiyun ppc4xx_hsta_msi.irq_map[irq] =
165*4882a593Smuzhiyun irq_of_parse_and_map(dev->of_node, irq);
166*4882a593Smuzhiyun if (!ppc4xx_hsta_msi.irq_map[irq]) {
167*4882a593Smuzhiyun dev_err(dev, "Unable to map IRQ\n");
168*4882a593Smuzhiyun ret = -EINVAL;
169*4882a593Smuzhiyun goto out2;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun list_for_each_entry(phb, &hose_list, list_node) {
174*4882a593Smuzhiyun phb->controller_ops.setup_msi_irqs = hsta_setup_msi_irqs;
175*4882a593Smuzhiyun phb->controller_ops.teardown_msi_irqs = hsta_teardown_msi_irqs;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun return 0;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun out2:
180*4882a593Smuzhiyun kfree(ppc4xx_hsta_msi.irq_map);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun out1:
183*4882a593Smuzhiyun msi_bitmap_free(&ppc4xx_hsta_msi.bmp);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun out:
186*4882a593Smuzhiyun iounmap(ppc4xx_hsta_msi.data);
187*4882a593Smuzhiyun return ret;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun static const struct of_device_id hsta_msi_ids[] = {
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun .compatible = "ibm,hsta-msi",
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun {}
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static struct platform_driver hsta_msi_driver = {
198*4882a593Smuzhiyun .probe = hsta_msi_probe,
199*4882a593Smuzhiyun .driver = {
200*4882a593Smuzhiyun .name = "hsta-msi",
201*4882a593Smuzhiyun .of_match_table = hsta_msi_ids,
202*4882a593Smuzhiyun },
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun
hsta_msi_init(void)205*4882a593Smuzhiyun static int hsta_msi_init(void)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun return platform_driver_register(&hsta_msi_driver);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun subsys_initcall(hsta_msi_init);
210