1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Performance counter support for POWER9 processors. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Power9 event codes. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun EVENT(PM_CYC, 0x0001e) 12*4882a593Smuzhiyun EVENT(PM_ICT_NOSLOT_CYC, 0x100f8) 13*4882a593Smuzhiyun EVENT(PM_CMPLU_STALL, 0x1e054) 14*4882a593Smuzhiyun EVENT(PM_INST_CMPL, 0x00002) 15*4882a593Smuzhiyun EVENT(PM_BR_CMPL, 0x4d05e) 16*4882a593Smuzhiyun EVENT(PM_BR_MPRED_CMPL, 0x400f6) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* All L1 D cache load references counted at finish, gated by reject */ 19*4882a593Smuzhiyun EVENT(PM_LD_REF_L1, 0x100fc) 20*4882a593Smuzhiyun /* Load Missed L1 */ 21*4882a593Smuzhiyun EVENT(PM_LD_MISS_L1_FIN, 0x2c04e) 22*4882a593Smuzhiyun EVENT(PM_LD_MISS_L1, 0x3e054) 23*4882a593Smuzhiyun /* Alternate event code for PM_LD_MISS_L1 */ 24*4882a593Smuzhiyun EVENT(PM_LD_MISS_L1_ALT, 0x400f0) 25*4882a593Smuzhiyun /* Store Missed L1 */ 26*4882a593Smuzhiyun EVENT(PM_ST_MISS_L1, 0x300f0) 27*4882a593Smuzhiyun /* L1 cache data prefetches */ 28*4882a593Smuzhiyun EVENT(PM_L1_PREF, 0x20054) 29*4882a593Smuzhiyun /* Instruction fetches from L1 */ 30*4882a593Smuzhiyun EVENT(PM_INST_FROM_L1, 0x04080) 31*4882a593Smuzhiyun /* Demand iCache Miss */ 32*4882a593Smuzhiyun EVENT(PM_L1_ICACHE_MISS, 0x200fd) 33*4882a593Smuzhiyun /* Instruction Demand sectors wriittent into IL1 */ 34*4882a593Smuzhiyun EVENT(PM_L1_DEMAND_WRITE, 0x0408c) 35*4882a593Smuzhiyun /* Instruction prefetch written into IL1 */ 36*4882a593Smuzhiyun EVENT(PM_IC_PREF_WRITE, 0x0488c) 37*4882a593Smuzhiyun /* The data cache was reloaded from local core's L3 due to a demand load */ 38*4882a593Smuzhiyun EVENT(PM_DATA_FROM_L3, 0x4c042) 39*4882a593Smuzhiyun /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 40*4882a593Smuzhiyun EVENT(PM_DATA_FROM_L3MISS, 0x300fe) 41*4882a593Smuzhiyun /* All successful D-side store dispatches for this thread */ 42*4882a593Smuzhiyun EVENT(PM_L2_ST, 0x16880) 43*4882a593Smuzhiyun /* All successful D-side store dispatches for this thread that were L2 Miss */ 44*4882a593Smuzhiyun EVENT(PM_L2_ST_MISS, 0x26880) 45*4882a593Smuzhiyun /* Total HW L3 prefetches(Load+store) */ 46*4882a593Smuzhiyun EVENT(PM_L3_PREF_ALL, 0x4e052) 47*4882a593Smuzhiyun /* Data PTEG reload */ 48*4882a593Smuzhiyun EVENT(PM_DTLB_MISS, 0x300fc) 49*4882a593Smuzhiyun /* ITLB Reloaded */ 50*4882a593Smuzhiyun EVENT(PM_ITLB_MISS, 0x400fc) 51*4882a593Smuzhiyun /* Run_Instructions */ 52*4882a593Smuzhiyun EVENT(PM_RUN_INST_CMPL, 0x500fa) 53*4882a593Smuzhiyun /* Alternate event code for PM_RUN_INST_CMPL */ 54*4882a593Smuzhiyun EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa) 55*4882a593Smuzhiyun /* Run_cycles */ 56*4882a593Smuzhiyun EVENT(PM_RUN_CYC, 0x600f4) 57*4882a593Smuzhiyun /* Alternate event code for Run_cycles */ 58*4882a593Smuzhiyun EVENT(PM_RUN_CYC_ALT, 0x200f4) 59*4882a593Smuzhiyun /* Instruction Dispatched */ 60*4882a593Smuzhiyun EVENT(PM_INST_DISP, 0x200f2) 61*4882a593Smuzhiyun EVENT(PM_INST_DISP_ALT, 0x300f2) 62*4882a593Smuzhiyun /* Branch event that are not strongly biased */ 63*4882a593Smuzhiyun EVENT(PM_BR_2PATH, 0x20036) 64*4882a593Smuzhiyun /* ALternate branch event that are not strongly biased */ 65*4882a593Smuzhiyun EVENT(PM_BR_2PATH_ALT, 0x40036) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Blacklisted events */ 68*4882a593Smuzhiyun EVENT(PM_MRK_ST_DONE_L2, 0x10134) 69*4882a593Smuzhiyun EVENT(PM_RADIX_PWC_L1_HIT, 0x1f056) 70*4882a593Smuzhiyun EVENT(PM_FLOP_CMPL, 0x100f4) 71*4882a593Smuzhiyun EVENT(PM_MRK_NTF_FIN, 0x20112) 72*4882a593Smuzhiyun EVENT(PM_RADIX_PWC_L2_HIT, 0x2d024) 73*4882a593Smuzhiyun EVENT(PM_IFETCH_THROTTLE, 0x3405e) 74*4882a593Smuzhiyun EVENT(PM_MRK_L2_TM_ST_ABORT_SISTER, 0x3e15c) 75*4882a593Smuzhiyun EVENT(PM_RADIX_PWC_L3_HIT, 0x3f056) 76*4882a593Smuzhiyun EVENT(PM_RUN_CYC_SMT2_MODE, 0x3006c) 77*4882a593Smuzhiyun EVENT(PM_TM_TX_PASS_RUN_INST, 0x4e014) 78*4882a593Smuzhiyun EVENT(PM_DISP_HELD_SYNC_HOLD, 0x4003c) 79*4882a593Smuzhiyun EVENT(PM_DTLB_MISS_16G, 0x1c058) 80*4882a593Smuzhiyun EVENT(PM_DERAT_MISS_2M, 0x1c05a) 81*4882a593Smuzhiyun EVENT(PM_DTLB_MISS_2M, 0x1c05c) 82*4882a593Smuzhiyun EVENT(PM_MRK_DTLB_MISS_1G, 0x1d15c) 83*4882a593Smuzhiyun EVENT(PM_DTLB_MISS_4K, 0x2c056) 84*4882a593Smuzhiyun EVENT(PM_DERAT_MISS_1G, 0x2c05a) 85*4882a593Smuzhiyun EVENT(PM_MRK_DERAT_MISS_2M, 0x2d152) 86*4882a593Smuzhiyun EVENT(PM_MRK_DTLB_MISS_4K, 0x2d156) 87*4882a593Smuzhiyun EVENT(PM_MRK_DTLB_MISS_16G, 0x2d15e) 88*4882a593Smuzhiyun EVENT(PM_DTLB_MISS_64K, 0x3c056) 89*4882a593Smuzhiyun EVENT(PM_MRK_DERAT_MISS_1G, 0x3d152) 90*4882a593Smuzhiyun EVENT(PM_MRK_DTLB_MISS_64K, 0x3d156) 91*4882a593Smuzhiyun EVENT(PM_DTLB_MISS_16M, 0x4c056) 92*4882a593Smuzhiyun EVENT(PM_DTLB_MISS_1G, 0x4c05a) 93*4882a593Smuzhiyun EVENT(PM_MRK_DTLB_MISS_16M, 0x4c15e) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * Memory Access Events 97*4882a593Smuzhiyun * 98*4882a593Smuzhiyun * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) 99*4882a593Smuzhiyun * To enable capturing of memory profiling, these MMCRA bits 100*4882a593Smuzhiyun * needs to be programmed and corresponding raw event format 101*4882a593Smuzhiyun * encoding. 102*4882a593Smuzhiyun * 103*4882a593Smuzhiyun * MMCRA bits encoding needed are 104*4882a593Smuzhiyun * SM (Sampling Mode) 105*4882a593Smuzhiyun * EM (Eligibility for Random Sampling) 106*4882a593Smuzhiyun * TECE (Threshold Event Counter Event) 107*4882a593Smuzhiyun * TS (Threshold Start Event) 108*4882a593Smuzhiyun * TE (Threshold End Event) 109*4882a593Smuzhiyun * 110*4882a593Smuzhiyun * Corresponding Raw Encoding bits: 111*4882a593Smuzhiyun * sample [EM,SM] 112*4882a593Smuzhiyun * thresh_sel (TECE) 113*4882a593Smuzhiyun * thresh start (TS) 114*4882a593Smuzhiyun * thresh end (TE) 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun EVENT(MEM_LOADS, 0x34340401e0) 117*4882a593Smuzhiyun EVENT(MEM_STORES, 0x343c0401e0) 118