1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Performance counter support for POWER8 processors. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2014 Sukadev Bhattiprolu, IBM Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Power8 event codes. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun EVENT(PM_CYC, 0x0001e) 12*4882a593Smuzhiyun EVENT(PM_GCT_NOSLOT_CYC, 0x100f8) 13*4882a593Smuzhiyun EVENT(PM_CMPLU_STALL, 0x4000a) 14*4882a593Smuzhiyun EVENT(PM_INST_CMPL, 0x00002) 15*4882a593Smuzhiyun EVENT(PM_BRU_FIN, 0x10068) 16*4882a593Smuzhiyun EVENT(PM_BR_MPRED_CMPL, 0x400f6) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* All L1 D cache load references counted at finish, gated by reject */ 19*4882a593Smuzhiyun EVENT(PM_LD_REF_L1, 0x100ee) 20*4882a593Smuzhiyun /* Load Missed L1 */ 21*4882a593Smuzhiyun EVENT(PM_LD_MISS_L1, 0x3e054) 22*4882a593Smuzhiyun /* Store Missed L1 */ 23*4882a593Smuzhiyun EVENT(PM_ST_MISS_L1, 0x300f0) 24*4882a593Smuzhiyun /* L1 cache data prefetches */ 25*4882a593Smuzhiyun EVENT(PM_L1_PREF, 0x0d8b8) 26*4882a593Smuzhiyun /* Instruction fetches from L1 */ 27*4882a593Smuzhiyun EVENT(PM_INST_FROM_L1, 0x04080) 28*4882a593Smuzhiyun /* Demand iCache Miss */ 29*4882a593Smuzhiyun EVENT(PM_L1_ICACHE_MISS, 0x200fd) 30*4882a593Smuzhiyun /* Instruction Demand sectors wriittent into IL1 */ 31*4882a593Smuzhiyun EVENT(PM_L1_DEMAND_WRITE, 0x0408c) 32*4882a593Smuzhiyun /* Instruction prefetch written into IL1 */ 33*4882a593Smuzhiyun EVENT(PM_IC_PREF_WRITE, 0x0408e) 34*4882a593Smuzhiyun /* The data cache was reloaded from local core's L3 due to a demand load */ 35*4882a593Smuzhiyun EVENT(PM_DATA_FROM_L3, 0x4c042) 36*4882a593Smuzhiyun /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 37*4882a593Smuzhiyun EVENT(PM_DATA_FROM_L3MISS, 0x300fe) 38*4882a593Smuzhiyun /* All successful D-side store dispatches for this thread */ 39*4882a593Smuzhiyun EVENT(PM_L2_ST, 0x17080) 40*4882a593Smuzhiyun /* All successful D-side store dispatches for this thread that were L2 Miss */ 41*4882a593Smuzhiyun EVENT(PM_L2_ST_MISS, 0x17082) 42*4882a593Smuzhiyun /* Total HW L3 prefetches(Load+store) */ 43*4882a593Smuzhiyun EVENT(PM_L3_PREF_ALL, 0x4e052) 44*4882a593Smuzhiyun /* Data PTEG reload */ 45*4882a593Smuzhiyun EVENT(PM_DTLB_MISS, 0x300fc) 46*4882a593Smuzhiyun /* ITLB Reloaded */ 47*4882a593Smuzhiyun EVENT(PM_ITLB_MISS, 0x400fc) 48*4882a593Smuzhiyun /* Run_Instructions */ 49*4882a593Smuzhiyun EVENT(PM_RUN_INST_CMPL, 0x500fa) 50*4882a593Smuzhiyun /* Alternate event code for PM_RUN_INST_CMPL */ 51*4882a593Smuzhiyun EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa) 52*4882a593Smuzhiyun /* Run_cycles */ 53*4882a593Smuzhiyun EVENT(PM_RUN_CYC, 0x600f4) 54*4882a593Smuzhiyun /* Alternate event code for Run_cycles */ 55*4882a593Smuzhiyun EVENT(PM_RUN_CYC_ALT, 0x200f4) 56*4882a593Smuzhiyun /* Marked store completed */ 57*4882a593Smuzhiyun EVENT(PM_MRK_ST_CMPL, 0x10134) 58*4882a593Smuzhiyun /* Alternate event code for Marked store completed */ 59*4882a593Smuzhiyun EVENT(PM_MRK_ST_CMPL_ALT, 0x301e2) 60*4882a593Smuzhiyun /* Marked two path branch */ 61*4882a593Smuzhiyun EVENT(PM_BR_MRK_2PATH, 0x10138) 62*4882a593Smuzhiyun /* Alternate event code for PM_BR_MRK_2PATH */ 63*4882a593Smuzhiyun EVENT(PM_BR_MRK_2PATH_ALT, 0x40138) 64*4882a593Smuzhiyun /* L3 castouts in Mepf state */ 65*4882a593Smuzhiyun EVENT(PM_L3_CO_MEPF, 0x18082) 66*4882a593Smuzhiyun /* Alternate event code for PM_L3_CO_MEPF */ 67*4882a593Smuzhiyun EVENT(PM_L3_CO_MEPF_ALT, 0x3e05e) 68*4882a593Smuzhiyun /* Data cache was reloaded from a location other than L2 due to a marked load */ 69*4882a593Smuzhiyun EVENT(PM_MRK_DATA_FROM_L2MISS, 0x1d14e) 70*4882a593Smuzhiyun /* Alternate event code for PM_MRK_DATA_FROM_L2MISS */ 71*4882a593Smuzhiyun EVENT(PM_MRK_DATA_FROM_L2MISS_ALT, 0x401e8) 72*4882a593Smuzhiyun /* Alternate event code for PM_CMPLU_STALL */ 73*4882a593Smuzhiyun EVENT(PM_CMPLU_STALL_ALT, 0x1e054) 74*4882a593Smuzhiyun /* Two path branch */ 75*4882a593Smuzhiyun EVENT(PM_BR_2PATH, 0x20036) 76*4882a593Smuzhiyun /* Alternate event code for PM_BR_2PATH */ 77*4882a593Smuzhiyun EVENT(PM_BR_2PATH_ALT, 0x40036) 78*4882a593Smuzhiyun /* # PPC Dispatched */ 79*4882a593Smuzhiyun EVENT(PM_INST_DISP, 0x200f2) 80*4882a593Smuzhiyun /* Alternate event code for PM_INST_DISP */ 81*4882a593Smuzhiyun EVENT(PM_INST_DISP_ALT, 0x300f2) 82*4882a593Smuzhiyun /* Marked filter Match */ 83*4882a593Smuzhiyun EVENT(PM_MRK_FILT_MATCH, 0x2013c) 84*4882a593Smuzhiyun /* Alternate event code for PM_MRK_FILT_MATCH */ 85*4882a593Smuzhiyun EVENT(PM_MRK_FILT_MATCH_ALT, 0x3012e) 86*4882a593Smuzhiyun /* Alternate event code for PM_LD_MISS_L1 */ 87*4882a593Smuzhiyun EVENT(PM_LD_MISS_L1_ALT, 0x400f0) 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * Memory Access Event -- mem_access 90*4882a593Smuzhiyun * Primary PMU event used here is PM_MRK_INST_CMPL, along with 91*4882a593Smuzhiyun * Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]). 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun EVENT(MEM_ACCESS, 0x10401e0) 94