1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Performance counter support for POWER10 processors. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2020 Madhavan Srinivasan, IBM Corporation. 6*4882a593Smuzhiyun * Copyright 2020 Athira Rajeev, IBM Corporation. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * Power10 event codes. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun EVENT(PM_RUN_CYC, 0x600f4); 13*4882a593Smuzhiyun EVENT(PM_DISP_STALL_CYC, 0x100f8); 14*4882a593Smuzhiyun EVENT(PM_EXEC_STALL, 0x30008); 15*4882a593Smuzhiyun EVENT(PM_RUN_INST_CMPL, 0x500fa); 16*4882a593Smuzhiyun EVENT(PM_BR_CMPL, 0x4d05e); 17*4882a593Smuzhiyun EVENT(PM_BR_MPRED_CMPL, 0x400f6); 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* All L1 D cache load references counted at finish, gated by reject */ 20*4882a593Smuzhiyun EVENT(PM_LD_REF_L1, 0x100fc); 21*4882a593Smuzhiyun /* Load Missed L1 */ 22*4882a593Smuzhiyun EVENT(PM_LD_MISS_L1, 0x3e054); 23*4882a593Smuzhiyun /* Store Missed L1 */ 24*4882a593Smuzhiyun EVENT(PM_ST_MISS_L1, 0x300f0); 25*4882a593Smuzhiyun /* L1 cache data prefetches */ 26*4882a593Smuzhiyun EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c); 27*4882a593Smuzhiyun /* Demand iCache Miss */ 28*4882a593Smuzhiyun EVENT(PM_L1_ICACHE_MISS, 0x200fc); 29*4882a593Smuzhiyun /* Instruction fetches from L1 */ 30*4882a593Smuzhiyun EVENT(PM_INST_FROM_L1, 0x04080); 31*4882a593Smuzhiyun /* Instruction Demand sectors wriittent into IL1 */ 32*4882a593Smuzhiyun EVENT(PM_INST_FROM_L1MISS, 0x03f00000001c040); 33*4882a593Smuzhiyun /* Instruction prefetch written into IL1 */ 34*4882a593Smuzhiyun EVENT(PM_IC_PREF_REQ, 0x040a0); 35*4882a593Smuzhiyun /* The data cache was reloaded from local core's L3 due to a demand load */ 36*4882a593Smuzhiyun EVENT(PM_DATA_FROM_L3, 0x01340000001c040); 37*4882a593Smuzhiyun /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 38*4882a593Smuzhiyun EVENT(PM_DATA_FROM_L3MISS, 0x300fe); 39*4882a593Smuzhiyun /* Data PTEG reload */ 40*4882a593Smuzhiyun EVENT(PM_DTLB_MISS, 0x300fc); 41*4882a593Smuzhiyun /* ITLB Reloaded */ 42*4882a593Smuzhiyun EVENT(PM_ITLB_MISS, 0x400fc); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun EVENT(PM_RUN_CYC_ALT, 0x0001e); 45*4882a593Smuzhiyun EVENT(PM_RUN_INST_CMPL_ALT, 0x00002); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * Memory Access Events 49*4882a593Smuzhiyun * 50*4882a593Smuzhiyun * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) 51*4882a593Smuzhiyun * To enable capturing of memory profiling, these MMCRA bits 52*4882a593Smuzhiyun * needs to be programmed and corresponding raw event format 53*4882a593Smuzhiyun * encoding. 54*4882a593Smuzhiyun * 55*4882a593Smuzhiyun * MMCRA bits encoding needed are 56*4882a593Smuzhiyun * SM (Sampling Mode) 57*4882a593Smuzhiyun * EM (Eligibility for Random Sampling) 58*4882a593Smuzhiyun * TECE (Threshold Event Counter Event) 59*4882a593Smuzhiyun * TS (Threshold Start Event) 60*4882a593Smuzhiyun * TE (Threshold End Event) 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun * Corresponding Raw Encoding bits: 63*4882a593Smuzhiyun * sample [EM,SM] 64*4882a593Smuzhiyun * thresh_sel (TECE) 65*4882a593Smuzhiyun * thresh start (TS) 66*4882a593Smuzhiyun * thresh end (TE) 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun EVENT(MEM_LOADS, 0x35340401e0); 70*4882a593Smuzhiyun EVENT(MEM_STORES, 0x353c0401e0); 71