1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Performance counter support for e6500 family processors.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Priyanka Jain, Priyanka.Jain@freescale.com
6*4882a593Smuzhiyun * Based on e500-pmu.c
7*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
8*4882a593Smuzhiyun * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/string.h>
12*4882a593Smuzhiyun #include <linux/perf_event.h>
13*4882a593Smuzhiyun #include <asm/reg.h>
14*4882a593Smuzhiyun #include <asm/cputable.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * Map of generic hardware event types to hardware events
18*4882a593Smuzhiyun * Zero if unsupported
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun static int e6500_generic_events[] = {
21*4882a593Smuzhiyun [PERF_COUNT_HW_CPU_CYCLES] = 1,
22*4882a593Smuzhiyun [PERF_COUNT_HW_INSTRUCTIONS] = 2,
23*4882a593Smuzhiyun [PERF_COUNT_HW_CACHE_MISSES] = 221,
24*4882a593Smuzhiyun [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
25*4882a593Smuzhiyun [PERF_COUNT_HW_BRANCH_MISSES] = 15,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define C(x) PERF_COUNT_HW_CACHE_##x
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Table of generalized cache-related events.
32*4882a593Smuzhiyun * 0 means not supported, -1 means nonsensical, other values
33*4882a593Smuzhiyun * are event codes.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36*4882a593Smuzhiyun [C(L1D)] = {
37*4882a593Smuzhiyun /*RESULT_ACCESS RESULT_MISS */
38*4882a593Smuzhiyun [C(OP_READ)] = { 27, 222 },
39*4882a593Smuzhiyun [C(OP_WRITE)] = { 28, 223 },
40*4882a593Smuzhiyun [C(OP_PREFETCH)] = { 29, 0 },
41*4882a593Smuzhiyun },
42*4882a593Smuzhiyun [C(L1I)] = {
43*4882a593Smuzhiyun /*RESULT_ACCESS RESULT_MISS */
44*4882a593Smuzhiyun [C(OP_READ)] = { 2, 254 },
45*4882a593Smuzhiyun [C(OP_WRITE)] = { -1, -1 },
46*4882a593Smuzhiyun [C(OP_PREFETCH)] = { 37, 0 },
47*4882a593Smuzhiyun },
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Assuming LL means L2, it's not a good match for this model.
50*4882a593Smuzhiyun * It does not have separate read/write events (but it does have
51*4882a593Smuzhiyun * separate instruction/data events).
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun [C(LL)] = {
54*4882a593Smuzhiyun /*RESULT_ACCESS RESULT_MISS */
55*4882a593Smuzhiyun [C(OP_READ)] = { 0, 0 },
56*4882a593Smuzhiyun [C(OP_WRITE)] = { 0, 0 },
57*4882a593Smuzhiyun [C(OP_PREFETCH)] = { 0, 0 },
58*4882a593Smuzhiyun },
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * There are data/instruction MMU misses, but that's a miss on
61*4882a593Smuzhiyun * the chip's internal level-one TLB which is probably not
62*4882a593Smuzhiyun * what the user wants. Instead, unified level-two TLB misses
63*4882a593Smuzhiyun * are reported here.
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun [C(DTLB)] = {
66*4882a593Smuzhiyun /*RESULT_ACCESS RESULT_MISS */
67*4882a593Smuzhiyun [C(OP_READ)] = { 26, 66 },
68*4882a593Smuzhiyun [C(OP_WRITE)] = { -1, -1 },
69*4882a593Smuzhiyun [C(OP_PREFETCH)] = { -1, -1 },
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun [C(BPU)] = {
72*4882a593Smuzhiyun /*RESULT_ACCESS RESULT_MISS */
73*4882a593Smuzhiyun [C(OP_READ)] = { 12, 15 },
74*4882a593Smuzhiyun [C(OP_WRITE)] = { -1, -1 },
75*4882a593Smuzhiyun [C(OP_PREFETCH)] = { -1, -1 },
76*4882a593Smuzhiyun },
77*4882a593Smuzhiyun [C(NODE)] = {
78*4882a593Smuzhiyun /* RESULT_ACCESS RESULT_MISS */
79*4882a593Smuzhiyun [C(OP_READ)] = { -1, -1 },
80*4882a593Smuzhiyun [C(OP_WRITE)] = { -1, -1 },
81*4882a593Smuzhiyun [C(OP_PREFETCH)] = { -1, -1 },
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static int num_events = 512;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Upper half of event id is PMLCb, for threshold events */
e6500_xlate_event(u64 event_id)88*4882a593Smuzhiyun static u64 e6500_xlate_event(u64 event_id)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun u32 event_low = (u32)event_id;
91*4882a593Smuzhiyun if (event_low >= num_events ||
92*4882a593Smuzhiyun (event_id & (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)))
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return FSL_EMB_EVENT_VALID;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct fsl_emb_pmu e6500_pmu = {
99*4882a593Smuzhiyun .name = "e6500 family",
100*4882a593Smuzhiyun .n_counter = 6,
101*4882a593Smuzhiyun .n_restricted = 0,
102*4882a593Smuzhiyun .xlate_event = e6500_xlate_event,
103*4882a593Smuzhiyun .n_generic = ARRAY_SIZE(e6500_generic_events),
104*4882a593Smuzhiyun .generic_events = e6500_generic_events,
105*4882a593Smuzhiyun .cache_events = &e6500_cache_events,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
init_e6500_pmu(void)108*4882a593Smuzhiyun static int init_e6500_pmu(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun if (!cur_cpu_spec->oprofile_cpu_type ||
111*4882a593Smuzhiyun strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e6500"))
112*4882a593Smuzhiyun return -ENODEV;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return register_fsl_emb_pmu(&e6500_pmu);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun early_initcall(init_e6500_pmu);
118