1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright IBM Corp. 2008
5*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors: Hollis Blanchard <hollisb@us.ibm.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kvm_host.h>
11*4882a593Smuzhiyun #include <asm/disassemble.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "booke.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define OP_19_XOP_RFI 50
16*4882a593Smuzhiyun #define OP_19_XOP_RFCI 51
17*4882a593Smuzhiyun #define OP_19_XOP_RFDI 39
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define OP_31_XOP_MFMSR 83
20*4882a593Smuzhiyun #define OP_31_XOP_WRTEE 131
21*4882a593Smuzhiyun #define OP_31_XOP_MTMSR 146
22*4882a593Smuzhiyun #define OP_31_XOP_WRTEEI 163
23*4882a593Smuzhiyun
kvmppc_emul_rfi(struct kvm_vcpu * vcpu)24*4882a593Smuzhiyun static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
27*4882a593Smuzhiyun kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
kvmppc_emul_rfdi(struct kvm_vcpu * vcpu)30*4882a593Smuzhiyun static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun vcpu->arch.regs.nip = vcpu->arch.dsrr0;
33*4882a593Smuzhiyun kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
kvmppc_emul_rfci(struct kvm_vcpu * vcpu)36*4882a593Smuzhiyun static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun vcpu->arch.regs.nip = vcpu->arch.csrr0;
39*4882a593Smuzhiyun kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
kvmppc_booke_emulate_op(struct kvm_vcpu * vcpu,unsigned int inst,int * advance)42*4882a593Smuzhiyun int kvmppc_booke_emulate_op(struct kvm_vcpu *vcpu,
43*4882a593Smuzhiyun unsigned int inst, int *advance)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun int emulated = EMULATE_DONE;
46*4882a593Smuzhiyun int rs = get_rs(inst);
47*4882a593Smuzhiyun int rt = get_rt(inst);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun switch (get_op(inst)) {
50*4882a593Smuzhiyun case 19:
51*4882a593Smuzhiyun switch (get_xop(inst)) {
52*4882a593Smuzhiyun case OP_19_XOP_RFI:
53*4882a593Smuzhiyun kvmppc_emul_rfi(vcpu);
54*4882a593Smuzhiyun kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
55*4882a593Smuzhiyun *advance = 0;
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun case OP_19_XOP_RFCI:
59*4882a593Smuzhiyun kvmppc_emul_rfci(vcpu);
60*4882a593Smuzhiyun kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
61*4882a593Smuzhiyun *advance = 0;
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun case OP_19_XOP_RFDI:
65*4882a593Smuzhiyun kvmppc_emul_rfdi(vcpu);
66*4882a593Smuzhiyun kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
67*4882a593Smuzhiyun *advance = 0;
68*4882a593Smuzhiyun break;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun default:
71*4882a593Smuzhiyun emulated = EMULATE_FAIL;
72*4882a593Smuzhiyun break;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun case 31:
77*4882a593Smuzhiyun switch (get_xop(inst)) {
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun case OP_31_XOP_MFMSR:
80*4882a593Smuzhiyun kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
81*4882a593Smuzhiyun kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun case OP_31_XOP_MTMSR:
85*4882a593Smuzhiyun kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
86*4882a593Smuzhiyun kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
87*4882a593Smuzhiyun break;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun case OP_31_XOP_WRTEE:
90*4882a593Smuzhiyun vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
91*4882a593Smuzhiyun | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
92*4882a593Smuzhiyun kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun case OP_31_XOP_WRTEEI:
96*4882a593Smuzhiyun vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
97*4882a593Smuzhiyun | (inst & MSR_EE);
98*4882a593Smuzhiyun kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
99*4882a593Smuzhiyun break;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun default:
102*4882a593Smuzhiyun emulated = EMULATE_FAIL;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun default:
108*4882a593Smuzhiyun emulated = EMULATE_FAIL;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return emulated;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
116*4882a593Smuzhiyun * Their backing store is in real registers, and these functions
117*4882a593Smuzhiyun * will return the wrong result if called for them in another context
118*4882a593Smuzhiyun * (such as debugging).
119*4882a593Smuzhiyun */
kvmppc_booke_emulate_mtspr(struct kvm_vcpu * vcpu,int sprn,ulong spr_val)120*4882a593Smuzhiyun int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun int emulated = EMULATE_DONE;
123*4882a593Smuzhiyun bool debug_inst = false;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun switch (sprn) {
126*4882a593Smuzhiyun case SPRN_DEAR:
127*4882a593Smuzhiyun vcpu->arch.shared->dar = spr_val;
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun case SPRN_ESR:
130*4882a593Smuzhiyun vcpu->arch.shared->esr = spr_val;
131*4882a593Smuzhiyun break;
132*4882a593Smuzhiyun case SPRN_CSRR0:
133*4882a593Smuzhiyun vcpu->arch.csrr0 = spr_val;
134*4882a593Smuzhiyun break;
135*4882a593Smuzhiyun case SPRN_CSRR1:
136*4882a593Smuzhiyun vcpu->arch.csrr1 = spr_val;
137*4882a593Smuzhiyun break;
138*4882a593Smuzhiyun case SPRN_DSRR0:
139*4882a593Smuzhiyun vcpu->arch.dsrr0 = spr_val;
140*4882a593Smuzhiyun break;
141*4882a593Smuzhiyun case SPRN_DSRR1:
142*4882a593Smuzhiyun vcpu->arch.dsrr1 = spr_val;
143*4882a593Smuzhiyun break;
144*4882a593Smuzhiyun case SPRN_IAC1:
145*4882a593Smuzhiyun /*
146*4882a593Smuzhiyun * If userspace is debugging guest then guest
147*4882a593Smuzhiyun * can not access debug registers.
148*4882a593Smuzhiyun */
149*4882a593Smuzhiyun if (vcpu->guest_debug)
150*4882a593Smuzhiyun break;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun debug_inst = true;
153*4882a593Smuzhiyun vcpu->arch.dbg_reg.iac1 = spr_val;
154*4882a593Smuzhiyun break;
155*4882a593Smuzhiyun case SPRN_IAC2:
156*4882a593Smuzhiyun /*
157*4882a593Smuzhiyun * If userspace is debugging guest then guest
158*4882a593Smuzhiyun * can not access debug registers.
159*4882a593Smuzhiyun */
160*4882a593Smuzhiyun if (vcpu->guest_debug)
161*4882a593Smuzhiyun break;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun debug_inst = true;
164*4882a593Smuzhiyun vcpu->arch.dbg_reg.iac2 = spr_val;
165*4882a593Smuzhiyun break;
166*4882a593Smuzhiyun #if CONFIG_PPC_ADV_DEBUG_IACS > 2
167*4882a593Smuzhiyun case SPRN_IAC3:
168*4882a593Smuzhiyun /*
169*4882a593Smuzhiyun * If userspace is debugging guest then guest
170*4882a593Smuzhiyun * can not access debug registers.
171*4882a593Smuzhiyun */
172*4882a593Smuzhiyun if (vcpu->guest_debug)
173*4882a593Smuzhiyun break;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun debug_inst = true;
176*4882a593Smuzhiyun vcpu->arch.dbg_reg.iac3 = spr_val;
177*4882a593Smuzhiyun break;
178*4882a593Smuzhiyun case SPRN_IAC4:
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun * If userspace is debugging guest then guest
181*4882a593Smuzhiyun * can not access debug registers.
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun if (vcpu->guest_debug)
184*4882a593Smuzhiyun break;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun debug_inst = true;
187*4882a593Smuzhiyun vcpu->arch.dbg_reg.iac4 = spr_val;
188*4882a593Smuzhiyun break;
189*4882a593Smuzhiyun #endif
190*4882a593Smuzhiyun case SPRN_DAC1:
191*4882a593Smuzhiyun /*
192*4882a593Smuzhiyun * If userspace is debugging guest then guest
193*4882a593Smuzhiyun * can not access debug registers.
194*4882a593Smuzhiyun */
195*4882a593Smuzhiyun if (vcpu->guest_debug)
196*4882a593Smuzhiyun break;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun debug_inst = true;
199*4882a593Smuzhiyun vcpu->arch.dbg_reg.dac1 = spr_val;
200*4882a593Smuzhiyun break;
201*4882a593Smuzhiyun case SPRN_DAC2:
202*4882a593Smuzhiyun /*
203*4882a593Smuzhiyun * If userspace is debugging guest then guest
204*4882a593Smuzhiyun * can not access debug registers.
205*4882a593Smuzhiyun */
206*4882a593Smuzhiyun if (vcpu->guest_debug)
207*4882a593Smuzhiyun break;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun debug_inst = true;
210*4882a593Smuzhiyun vcpu->arch.dbg_reg.dac2 = spr_val;
211*4882a593Smuzhiyun break;
212*4882a593Smuzhiyun case SPRN_DBCR0:
213*4882a593Smuzhiyun /*
214*4882a593Smuzhiyun * If userspace is debugging guest then guest
215*4882a593Smuzhiyun * can not access debug registers.
216*4882a593Smuzhiyun */
217*4882a593Smuzhiyun if (vcpu->guest_debug)
218*4882a593Smuzhiyun break;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun debug_inst = true;
221*4882a593Smuzhiyun spr_val &= (DBCR0_IDM | DBCR0_IC | DBCR0_BT | DBCR0_TIE |
222*4882a593Smuzhiyun DBCR0_IAC1 | DBCR0_IAC2 | DBCR0_IAC3 | DBCR0_IAC4 |
223*4882a593Smuzhiyun DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun vcpu->arch.dbg_reg.dbcr0 = spr_val;
226*4882a593Smuzhiyun break;
227*4882a593Smuzhiyun case SPRN_DBCR1:
228*4882a593Smuzhiyun /*
229*4882a593Smuzhiyun * If userspace is debugging guest then guest
230*4882a593Smuzhiyun * can not access debug registers.
231*4882a593Smuzhiyun */
232*4882a593Smuzhiyun if (vcpu->guest_debug)
233*4882a593Smuzhiyun break;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun debug_inst = true;
236*4882a593Smuzhiyun vcpu->arch.dbg_reg.dbcr1 = spr_val;
237*4882a593Smuzhiyun break;
238*4882a593Smuzhiyun case SPRN_DBCR2:
239*4882a593Smuzhiyun /*
240*4882a593Smuzhiyun * If userspace is debugging guest then guest
241*4882a593Smuzhiyun * can not access debug registers.
242*4882a593Smuzhiyun */
243*4882a593Smuzhiyun if (vcpu->guest_debug)
244*4882a593Smuzhiyun break;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun debug_inst = true;
247*4882a593Smuzhiyun vcpu->arch.dbg_reg.dbcr2 = spr_val;
248*4882a593Smuzhiyun break;
249*4882a593Smuzhiyun case SPRN_DBSR:
250*4882a593Smuzhiyun /*
251*4882a593Smuzhiyun * If userspace is debugging guest then guest
252*4882a593Smuzhiyun * can not access debug registers.
253*4882a593Smuzhiyun */
254*4882a593Smuzhiyun if (vcpu->guest_debug)
255*4882a593Smuzhiyun break;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun vcpu->arch.dbsr &= ~spr_val;
258*4882a593Smuzhiyun if (!(vcpu->arch.dbsr & ~DBSR_IDE))
259*4882a593Smuzhiyun kvmppc_core_dequeue_debug(vcpu);
260*4882a593Smuzhiyun break;
261*4882a593Smuzhiyun case SPRN_TSR:
262*4882a593Smuzhiyun kvmppc_clr_tsr_bits(vcpu, spr_val);
263*4882a593Smuzhiyun break;
264*4882a593Smuzhiyun case SPRN_TCR:
265*4882a593Smuzhiyun /*
266*4882a593Smuzhiyun * WRC is a 2-bit field that is supposed to preserve its
267*4882a593Smuzhiyun * value once written to non-zero.
268*4882a593Smuzhiyun */
269*4882a593Smuzhiyun if (vcpu->arch.tcr & TCR_WRC_MASK) {
270*4882a593Smuzhiyun spr_val &= ~TCR_WRC_MASK;
271*4882a593Smuzhiyun spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun kvmppc_set_tcr(vcpu, spr_val);
274*4882a593Smuzhiyun break;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun case SPRN_DECAR:
277*4882a593Smuzhiyun vcpu->arch.decar = spr_val;
278*4882a593Smuzhiyun break;
279*4882a593Smuzhiyun /*
280*4882a593Smuzhiyun * Note: SPRG4-7 are user-readable.
281*4882a593Smuzhiyun * These values are loaded into the real SPRGs when resuming the
282*4882a593Smuzhiyun * guest (PR-mode only).
283*4882a593Smuzhiyun */
284*4882a593Smuzhiyun case SPRN_SPRG4:
285*4882a593Smuzhiyun kvmppc_set_sprg4(vcpu, spr_val);
286*4882a593Smuzhiyun break;
287*4882a593Smuzhiyun case SPRN_SPRG5:
288*4882a593Smuzhiyun kvmppc_set_sprg5(vcpu, spr_val);
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun case SPRN_SPRG6:
291*4882a593Smuzhiyun kvmppc_set_sprg6(vcpu, spr_val);
292*4882a593Smuzhiyun break;
293*4882a593Smuzhiyun case SPRN_SPRG7:
294*4882a593Smuzhiyun kvmppc_set_sprg7(vcpu, spr_val);
295*4882a593Smuzhiyun break;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun case SPRN_IVPR:
298*4882a593Smuzhiyun vcpu->arch.ivpr = spr_val;
299*4882a593Smuzhiyun #ifdef CONFIG_KVM_BOOKE_HV
300*4882a593Smuzhiyun mtspr(SPRN_GIVPR, spr_val);
301*4882a593Smuzhiyun #endif
302*4882a593Smuzhiyun break;
303*4882a593Smuzhiyun case SPRN_IVOR0:
304*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
305*4882a593Smuzhiyun break;
306*4882a593Smuzhiyun case SPRN_IVOR1:
307*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
308*4882a593Smuzhiyun break;
309*4882a593Smuzhiyun case SPRN_IVOR2:
310*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
311*4882a593Smuzhiyun #ifdef CONFIG_KVM_BOOKE_HV
312*4882a593Smuzhiyun mtspr(SPRN_GIVOR2, spr_val);
313*4882a593Smuzhiyun #endif
314*4882a593Smuzhiyun break;
315*4882a593Smuzhiyun case SPRN_IVOR3:
316*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
317*4882a593Smuzhiyun break;
318*4882a593Smuzhiyun case SPRN_IVOR4:
319*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
320*4882a593Smuzhiyun break;
321*4882a593Smuzhiyun case SPRN_IVOR5:
322*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
323*4882a593Smuzhiyun break;
324*4882a593Smuzhiyun case SPRN_IVOR6:
325*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
326*4882a593Smuzhiyun break;
327*4882a593Smuzhiyun case SPRN_IVOR7:
328*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
329*4882a593Smuzhiyun break;
330*4882a593Smuzhiyun case SPRN_IVOR8:
331*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
332*4882a593Smuzhiyun #ifdef CONFIG_KVM_BOOKE_HV
333*4882a593Smuzhiyun mtspr(SPRN_GIVOR8, spr_val);
334*4882a593Smuzhiyun #endif
335*4882a593Smuzhiyun break;
336*4882a593Smuzhiyun case SPRN_IVOR9:
337*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
338*4882a593Smuzhiyun break;
339*4882a593Smuzhiyun case SPRN_IVOR10:
340*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
341*4882a593Smuzhiyun break;
342*4882a593Smuzhiyun case SPRN_IVOR11:
343*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
344*4882a593Smuzhiyun break;
345*4882a593Smuzhiyun case SPRN_IVOR12:
346*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
347*4882a593Smuzhiyun break;
348*4882a593Smuzhiyun case SPRN_IVOR13:
349*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
350*4882a593Smuzhiyun break;
351*4882a593Smuzhiyun case SPRN_IVOR14:
352*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
353*4882a593Smuzhiyun break;
354*4882a593Smuzhiyun case SPRN_IVOR15:
355*4882a593Smuzhiyun vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
356*4882a593Smuzhiyun break;
357*4882a593Smuzhiyun case SPRN_MCSR:
358*4882a593Smuzhiyun vcpu->arch.mcsr &= ~spr_val;
359*4882a593Smuzhiyun break;
360*4882a593Smuzhiyun #if defined(CONFIG_64BIT)
361*4882a593Smuzhiyun case SPRN_EPCR:
362*4882a593Smuzhiyun kvmppc_set_epcr(vcpu, spr_val);
363*4882a593Smuzhiyun #ifdef CONFIG_KVM_BOOKE_HV
364*4882a593Smuzhiyun mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
365*4882a593Smuzhiyun #endif
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun #endif
368*4882a593Smuzhiyun default:
369*4882a593Smuzhiyun emulated = EMULATE_FAIL;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun if (debug_inst) {
373*4882a593Smuzhiyun current->thread.debug = vcpu->arch.dbg_reg;
374*4882a593Smuzhiyun switch_booke_debug_regs(&vcpu->arch.dbg_reg);
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun return emulated;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
kvmppc_booke_emulate_mfspr(struct kvm_vcpu * vcpu,int sprn,ulong * spr_val)379*4882a593Smuzhiyun int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun int emulated = EMULATE_DONE;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun switch (sprn) {
384*4882a593Smuzhiyun case SPRN_IVPR:
385*4882a593Smuzhiyun *spr_val = vcpu->arch.ivpr;
386*4882a593Smuzhiyun break;
387*4882a593Smuzhiyun case SPRN_DEAR:
388*4882a593Smuzhiyun *spr_val = vcpu->arch.shared->dar;
389*4882a593Smuzhiyun break;
390*4882a593Smuzhiyun case SPRN_ESR:
391*4882a593Smuzhiyun *spr_val = vcpu->arch.shared->esr;
392*4882a593Smuzhiyun break;
393*4882a593Smuzhiyun case SPRN_EPR:
394*4882a593Smuzhiyun *spr_val = vcpu->arch.epr;
395*4882a593Smuzhiyun break;
396*4882a593Smuzhiyun case SPRN_CSRR0:
397*4882a593Smuzhiyun *spr_val = vcpu->arch.csrr0;
398*4882a593Smuzhiyun break;
399*4882a593Smuzhiyun case SPRN_CSRR1:
400*4882a593Smuzhiyun *spr_val = vcpu->arch.csrr1;
401*4882a593Smuzhiyun break;
402*4882a593Smuzhiyun case SPRN_DSRR0:
403*4882a593Smuzhiyun *spr_val = vcpu->arch.dsrr0;
404*4882a593Smuzhiyun break;
405*4882a593Smuzhiyun case SPRN_DSRR1:
406*4882a593Smuzhiyun *spr_val = vcpu->arch.dsrr1;
407*4882a593Smuzhiyun break;
408*4882a593Smuzhiyun case SPRN_IAC1:
409*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.iac1;
410*4882a593Smuzhiyun break;
411*4882a593Smuzhiyun case SPRN_IAC2:
412*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.iac2;
413*4882a593Smuzhiyun break;
414*4882a593Smuzhiyun #if CONFIG_PPC_ADV_DEBUG_IACS > 2
415*4882a593Smuzhiyun case SPRN_IAC3:
416*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.iac3;
417*4882a593Smuzhiyun break;
418*4882a593Smuzhiyun case SPRN_IAC4:
419*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.iac4;
420*4882a593Smuzhiyun break;
421*4882a593Smuzhiyun #endif
422*4882a593Smuzhiyun case SPRN_DAC1:
423*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.dac1;
424*4882a593Smuzhiyun break;
425*4882a593Smuzhiyun case SPRN_DAC2:
426*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.dac2;
427*4882a593Smuzhiyun break;
428*4882a593Smuzhiyun case SPRN_DBCR0:
429*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.dbcr0;
430*4882a593Smuzhiyun if (vcpu->guest_debug)
431*4882a593Smuzhiyun *spr_val = *spr_val | DBCR0_EDM;
432*4882a593Smuzhiyun break;
433*4882a593Smuzhiyun case SPRN_DBCR1:
434*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.dbcr1;
435*4882a593Smuzhiyun break;
436*4882a593Smuzhiyun case SPRN_DBCR2:
437*4882a593Smuzhiyun *spr_val = vcpu->arch.dbg_reg.dbcr2;
438*4882a593Smuzhiyun break;
439*4882a593Smuzhiyun case SPRN_DBSR:
440*4882a593Smuzhiyun *spr_val = vcpu->arch.dbsr;
441*4882a593Smuzhiyun break;
442*4882a593Smuzhiyun case SPRN_TSR:
443*4882a593Smuzhiyun *spr_val = vcpu->arch.tsr;
444*4882a593Smuzhiyun break;
445*4882a593Smuzhiyun case SPRN_TCR:
446*4882a593Smuzhiyun *spr_val = vcpu->arch.tcr;
447*4882a593Smuzhiyun break;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun case SPRN_IVOR0:
450*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
451*4882a593Smuzhiyun break;
452*4882a593Smuzhiyun case SPRN_IVOR1:
453*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
454*4882a593Smuzhiyun break;
455*4882a593Smuzhiyun case SPRN_IVOR2:
456*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
457*4882a593Smuzhiyun break;
458*4882a593Smuzhiyun case SPRN_IVOR3:
459*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
460*4882a593Smuzhiyun break;
461*4882a593Smuzhiyun case SPRN_IVOR4:
462*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
463*4882a593Smuzhiyun break;
464*4882a593Smuzhiyun case SPRN_IVOR5:
465*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
466*4882a593Smuzhiyun break;
467*4882a593Smuzhiyun case SPRN_IVOR6:
468*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
469*4882a593Smuzhiyun break;
470*4882a593Smuzhiyun case SPRN_IVOR7:
471*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
472*4882a593Smuzhiyun break;
473*4882a593Smuzhiyun case SPRN_IVOR8:
474*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
475*4882a593Smuzhiyun break;
476*4882a593Smuzhiyun case SPRN_IVOR9:
477*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
478*4882a593Smuzhiyun break;
479*4882a593Smuzhiyun case SPRN_IVOR10:
480*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
481*4882a593Smuzhiyun break;
482*4882a593Smuzhiyun case SPRN_IVOR11:
483*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
484*4882a593Smuzhiyun break;
485*4882a593Smuzhiyun case SPRN_IVOR12:
486*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
487*4882a593Smuzhiyun break;
488*4882a593Smuzhiyun case SPRN_IVOR13:
489*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
490*4882a593Smuzhiyun break;
491*4882a593Smuzhiyun case SPRN_IVOR14:
492*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
493*4882a593Smuzhiyun break;
494*4882a593Smuzhiyun case SPRN_IVOR15:
495*4882a593Smuzhiyun *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
496*4882a593Smuzhiyun break;
497*4882a593Smuzhiyun case SPRN_MCSR:
498*4882a593Smuzhiyun *spr_val = vcpu->arch.mcsr;
499*4882a593Smuzhiyun break;
500*4882a593Smuzhiyun #if defined(CONFIG_64BIT)
501*4882a593Smuzhiyun case SPRN_EPCR:
502*4882a593Smuzhiyun *spr_val = vcpu->arch.epcr;
503*4882a593Smuzhiyun break;
504*4882a593Smuzhiyun #endif
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun default:
507*4882a593Smuzhiyun emulated = EMULATE_FAIL;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun return emulated;
511*4882a593Smuzhiyun }
512