1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2*4882a593Smuzhiyun #ifndef _ASM_POWERPC_SIGCONTEXT_H 3*4882a593Smuzhiyun #define _ASM_POWERPC_SIGCONTEXT_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License 8*4882a593Smuzhiyun * as published by the Free Software Foundation; either version 9*4882a593Smuzhiyun * 2 of the License, or (at your option) any later version. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #include <linux/compiler.h> 12*4882a593Smuzhiyun #include <asm/ptrace.h> 13*4882a593Smuzhiyun #ifdef __powerpc64__ 14*4882a593Smuzhiyun #include <asm/elf.h> 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct sigcontext { 18*4882a593Smuzhiyun unsigned long _unused[4]; 19*4882a593Smuzhiyun int signal; 20*4882a593Smuzhiyun #ifdef __powerpc64__ 21*4882a593Smuzhiyun int _pad0; 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun unsigned long handler; 24*4882a593Smuzhiyun unsigned long oldmask; 25*4882a593Smuzhiyun #ifdef __KERNEL__ 26*4882a593Smuzhiyun struct user_pt_regs __user *regs; 27*4882a593Smuzhiyun #else 28*4882a593Smuzhiyun struct pt_regs *regs; 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun #ifdef __powerpc64__ 31*4882a593Smuzhiyun elf_gregset_t gp_regs; 32*4882a593Smuzhiyun elf_fpregset_t fp_regs; 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * To maintain compatibility with current implementations the sigcontext is 35*4882a593Smuzhiyun * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) 36*4882a593Smuzhiyun * followed by an unstructured (vmx_reserve) field of 101 doublewords. This 37*4882a593Smuzhiyun * allows the array of vector registers to be quadword aligned independent of 38*4882a593Smuzhiyun * the alignment of the containing sigcontext or ucontext. It is the 39*4882a593Smuzhiyun * responsibility of the code setting the sigcontext to set this pointer to 40*4882a593Smuzhiyun * either NULL (if this processor does not support the VMX feature) or the 41*4882a593Smuzhiyun * address of the first quadword within the allocated (vmx_reserve) area. 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with 44*4882a593Smuzhiyun * an array of 34 quadword entries (elf_vrregset_t). The entries with 45*4882a593Smuzhiyun * indexes 0-31 contain the corresponding vector registers. The entry with 46*4882a593Smuzhiyun * index 32 contains the vscr as the last word (offset 12) within the 47*4882a593Smuzhiyun * quadword. This allows the vscr to be stored as either a quadword (since 48*4882a593Smuzhiyun * it must be copied via a vector register to/from storage) or as a word. 49*4882a593Smuzhiyun * The entry with index 33 contains the vrsave as the first word (offset 0) 50*4882a593Smuzhiyun * within the quadword. 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * Part of the VSX data is stored here also by extending vmx_restore 53*4882a593Smuzhiyun * by an additional 32 double words. Architecturally the layout of 54*4882a593Smuzhiyun * the VSR registers and how they overlap on top of the legacy FPR and 55*4882a593Smuzhiyun * VR registers is shown below: 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun * VSR doubleword 0 VSR doubleword 1 58*4882a593Smuzhiyun * ---------------------------------------------------------------- 59*4882a593Smuzhiyun * VSR[0] | FPR[0] | | 60*4882a593Smuzhiyun * ---------------------------------------------------------------- 61*4882a593Smuzhiyun * VSR[1] | FPR[1] | | 62*4882a593Smuzhiyun * ---------------------------------------------------------------- 63*4882a593Smuzhiyun * | ... | | 64*4882a593Smuzhiyun * | ... | | 65*4882a593Smuzhiyun * ---------------------------------------------------------------- 66*4882a593Smuzhiyun * VSR[30] | FPR[30] | | 67*4882a593Smuzhiyun * ---------------------------------------------------------------- 68*4882a593Smuzhiyun * VSR[31] | FPR[31] | | 69*4882a593Smuzhiyun * ---------------------------------------------------------------- 70*4882a593Smuzhiyun * VSR[32] | VR[0] | 71*4882a593Smuzhiyun * ---------------------------------------------------------------- 72*4882a593Smuzhiyun * VSR[33] | VR[1] | 73*4882a593Smuzhiyun * ---------------------------------------------------------------- 74*4882a593Smuzhiyun * | ... | 75*4882a593Smuzhiyun * | ... | 76*4882a593Smuzhiyun * ---------------------------------------------------------------- 77*4882a593Smuzhiyun * VSR[62] | VR[30] | 78*4882a593Smuzhiyun * ---------------------------------------------------------------- 79*4882a593Smuzhiyun * VSR[63] | VR[31] | 80*4882a593Smuzhiyun * ---------------------------------------------------------------- 81*4882a593Smuzhiyun * 82*4882a593Smuzhiyun * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63 83*4882a593Smuzhiyun * is stored at the start of vmx_reserve. vmx_reserve is extended for 84*4882a593Smuzhiyun * backwards compatility to store VSR 0-31 doubleword 1 after the VMX 85*4882a593Smuzhiyun * registers and vscr/vrsave. 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun elf_vrreg_t __user *v_regs; 88*4882a593Smuzhiyun long vmx_reserve[ELF_NVRREG + ELF_NVRREG + 1 + 32]; 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* _ASM_POWERPC_SIGCONTEXT_H */ 93