1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun #ifndef _UAPI_ASM_POWERPC_PERF_REGS_H 3*4882a593Smuzhiyun #define _UAPI_ASM_POWERPC_PERF_REGS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun enum perf_event_powerpc_regs { 6*4882a593Smuzhiyun PERF_REG_POWERPC_R0, 7*4882a593Smuzhiyun PERF_REG_POWERPC_R1, 8*4882a593Smuzhiyun PERF_REG_POWERPC_R2, 9*4882a593Smuzhiyun PERF_REG_POWERPC_R3, 10*4882a593Smuzhiyun PERF_REG_POWERPC_R4, 11*4882a593Smuzhiyun PERF_REG_POWERPC_R5, 12*4882a593Smuzhiyun PERF_REG_POWERPC_R6, 13*4882a593Smuzhiyun PERF_REG_POWERPC_R7, 14*4882a593Smuzhiyun PERF_REG_POWERPC_R8, 15*4882a593Smuzhiyun PERF_REG_POWERPC_R9, 16*4882a593Smuzhiyun PERF_REG_POWERPC_R10, 17*4882a593Smuzhiyun PERF_REG_POWERPC_R11, 18*4882a593Smuzhiyun PERF_REG_POWERPC_R12, 19*4882a593Smuzhiyun PERF_REG_POWERPC_R13, 20*4882a593Smuzhiyun PERF_REG_POWERPC_R14, 21*4882a593Smuzhiyun PERF_REG_POWERPC_R15, 22*4882a593Smuzhiyun PERF_REG_POWERPC_R16, 23*4882a593Smuzhiyun PERF_REG_POWERPC_R17, 24*4882a593Smuzhiyun PERF_REG_POWERPC_R18, 25*4882a593Smuzhiyun PERF_REG_POWERPC_R19, 26*4882a593Smuzhiyun PERF_REG_POWERPC_R20, 27*4882a593Smuzhiyun PERF_REG_POWERPC_R21, 28*4882a593Smuzhiyun PERF_REG_POWERPC_R22, 29*4882a593Smuzhiyun PERF_REG_POWERPC_R23, 30*4882a593Smuzhiyun PERF_REG_POWERPC_R24, 31*4882a593Smuzhiyun PERF_REG_POWERPC_R25, 32*4882a593Smuzhiyun PERF_REG_POWERPC_R26, 33*4882a593Smuzhiyun PERF_REG_POWERPC_R27, 34*4882a593Smuzhiyun PERF_REG_POWERPC_R28, 35*4882a593Smuzhiyun PERF_REG_POWERPC_R29, 36*4882a593Smuzhiyun PERF_REG_POWERPC_R30, 37*4882a593Smuzhiyun PERF_REG_POWERPC_R31, 38*4882a593Smuzhiyun PERF_REG_POWERPC_NIP, 39*4882a593Smuzhiyun PERF_REG_POWERPC_MSR, 40*4882a593Smuzhiyun PERF_REG_POWERPC_ORIG_R3, 41*4882a593Smuzhiyun PERF_REG_POWERPC_CTR, 42*4882a593Smuzhiyun PERF_REG_POWERPC_LINK, 43*4882a593Smuzhiyun PERF_REG_POWERPC_XER, 44*4882a593Smuzhiyun PERF_REG_POWERPC_CCR, 45*4882a593Smuzhiyun PERF_REG_POWERPC_SOFTE, 46*4882a593Smuzhiyun PERF_REG_POWERPC_TRAP, 47*4882a593Smuzhiyun PERF_REG_POWERPC_DAR, 48*4882a593Smuzhiyun PERF_REG_POWERPC_DSISR, 49*4882a593Smuzhiyun PERF_REG_POWERPC_SIER, 50*4882a593Smuzhiyun PERF_REG_POWERPC_MMCRA, 51*4882a593Smuzhiyun /* Extended registers */ 52*4882a593Smuzhiyun PERF_REG_POWERPC_MMCR0, 53*4882a593Smuzhiyun PERF_REG_POWERPC_MMCR1, 54*4882a593Smuzhiyun PERF_REG_POWERPC_MMCR2, 55*4882a593Smuzhiyun PERF_REG_POWERPC_MMCR3, 56*4882a593Smuzhiyun PERF_REG_POWERPC_SIER2, 57*4882a593Smuzhiyun PERF_REG_POWERPC_SIER3, 58*4882a593Smuzhiyun /* Max regs without the extended regs */ 59*4882a593Smuzhiyun PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ 65*4882a593Smuzhiyun #define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK) 66*4882a593Smuzhiyun /* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */ 67*4882a593Smuzhiyun #define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1) 70*4882a593Smuzhiyun #define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1) 71*4882a593Smuzhiyun #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ 72