1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 4*4882a593Smuzhiyun * it under the terms of the GNU General Public License, version 2, as 5*4882a593Smuzhiyun * published by the Free Software Foundation. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 8*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 9*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10*4882a593Smuzhiyun * GNU General Public License for more details. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 13*4882a593Smuzhiyun * along with this program; if not, write to the Free Software 14*4882a593Smuzhiyun * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Copyright IBM Corp. 2015 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Authors: Gavin Shan <gwshan@linux.vnet.ibm.com> 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef _ASM_POWERPC_EEH_H 22*4882a593Smuzhiyun #define _ASM_POWERPC_EEH_H 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* PE states */ 25*4882a593Smuzhiyun #define EEH_PE_STATE_NORMAL 0 /* Normal state */ 26*4882a593Smuzhiyun #define EEH_PE_STATE_RESET 1 /* PE reset asserted */ 27*4882a593Smuzhiyun #define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */ 28*4882a593Smuzhiyun #define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */ 29*4882a593Smuzhiyun #define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* EEH error types and functions */ 32*4882a593Smuzhiyun #define EEH_ERR_TYPE_32 0 /* 32-bits error */ 33*4882a593Smuzhiyun #define EEH_ERR_TYPE_64 1 /* 64-bits error */ 34*4882a593Smuzhiyun #define EEH_ERR_FUNC_MIN 0 35*4882a593Smuzhiyun #define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */ 36*4882a593Smuzhiyun #define EEH_ERR_FUNC_LD_MEM_DATA 1 37*4882a593Smuzhiyun #define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */ 38*4882a593Smuzhiyun #define EEH_ERR_FUNC_LD_IO_DATA 3 39*4882a593Smuzhiyun #define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */ 40*4882a593Smuzhiyun #define EEH_ERR_FUNC_LD_CFG_DATA 5 41*4882a593Smuzhiyun #define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */ 42*4882a593Smuzhiyun #define EEH_ERR_FUNC_ST_MEM_DATA 7 43*4882a593Smuzhiyun #define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */ 44*4882a593Smuzhiyun #define EEH_ERR_FUNC_ST_IO_DATA 9 45*4882a593Smuzhiyun #define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */ 46*4882a593Smuzhiyun #define EEH_ERR_FUNC_ST_CFG_DATA 11 47*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */ 48*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_RD_DATA 13 49*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_RD_MASTER 14 50*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_RD_TARGET 15 51*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */ 52*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_WR_DATA 17 53*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_WR_MASTER 18 54*4882a593Smuzhiyun #define EEH_ERR_FUNC_DMA_WR_TARGET 19 55*4882a593Smuzhiyun #define EEH_ERR_FUNC_MAX 19 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* _ASM_POWERPC_EEH_H */ 58