1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2005 Tundra Semiconductor Corp. 4*4882a593Smuzhiyun * Alex Bounine, <alexandreb at tundra.com). 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * See file CREDITS for list of people who contributed to this 7*4882a593Smuzhiyun * project. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * definitions for interrupt controller initialization and external interrupt 12*4882a593Smuzhiyun * demultiplexing on TSI108EMU/SVB boards. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _ASM_POWERPC_TSI108_IRQ_H 16*4882a593Smuzhiyun #define _ASM_POWERPC_TSI108_IRQ_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Tsi108 interrupts 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #ifndef TSI108_IRQ_REG_BASE 22*4882a593Smuzhiyun #define TSI108_IRQ_REG_BASE 0 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x)) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */ 28*4882a593Smuzhiyun #define MAX_TASK_PRIO 0xF 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define DEFAULT_PRIO_LVL 10 /* initial priority level */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Interrupt vectors assignment to external and internal 35*4882a593Smuzhiyun * sources of requests. */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* EXTERNAL INTERRUPT SOURCES */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */ 40*4882a593Smuzhiyun #define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */ 41*4882a593Smuzhiyun #define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */ 42*4882a593Smuzhiyun #define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* INTERNAL INTERRUPT SOURCES */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */ 47*4882a593Smuzhiyun #define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */ 48*4882a593Smuzhiyun #define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */ 49*4882a593Smuzhiyun #define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */ 50*4882a593Smuzhiyun #define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */ 51*4882a593Smuzhiyun #define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */ 52*4882a593Smuzhiyun #define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */ 53*4882a593Smuzhiyun #define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */ 54*4882a593Smuzhiyun #define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */ 55*4882a593Smuzhiyun #define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */ 56*4882a593Smuzhiyun #define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */ 57*4882a593Smuzhiyun #define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */ 58*4882a593Smuzhiyun #define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */ 59*4882a593Smuzhiyun #define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */ 60*4882a593Smuzhiyun #define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */ 61*4882a593Smuzhiyun #define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */ 62*4882a593Smuzhiyun #define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */ 63*4882a593Smuzhiyun #define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */ 64*4882a593Smuzhiyun #define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */ 65*4882a593Smuzhiyun #define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */ 68*4882a593Smuzhiyun #define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */ 69*4882a593Smuzhiyun #define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */ 70*4882a593Smuzhiyun #define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */ 73*4882a593Smuzhiyun #define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */ 74*4882a593Smuzhiyun #define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */ 75*4882a593Smuzhiyun #define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */ 78*4882a593Smuzhiyun #define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */ 79*4882a593Smuzhiyun #define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */ 80*4882a593Smuzhiyun #define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * PCI bus INTA# - INTD# lines demultiplexor 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define IRQ_PCI_INTAD_BASE TSI108_IRQ(36) 86*4882a593Smuzhiyun #define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0) 87*4882a593Smuzhiyun #define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1) 88*4882a593Smuzhiyun #define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2) 89*4882a593Smuzhiyun #define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3) 90*4882a593Smuzhiyun #define NUM_PCI_IRQS (4) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* number of entries in vector dispatch table */ 93*4882a593Smuzhiyun #define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Mapping of MPIC outputs to processors' interrupt pins */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define IDIR_INT_OUT0 0x1 98*4882a593Smuzhiyun #define IDIR_INT_OUT1 0x2 99*4882a593Smuzhiyun #define IDIR_INT_OUT2 0x4 100*4882a593Smuzhiyun #define IDIR_INT_OUT3 0x8 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /*--------------------------------------------------------------- 103*4882a593Smuzhiyun * IRQ line configuration parameters */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Interrupt delivery modes */ 106*4882a593Smuzhiyun typedef enum { 107*4882a593Smuzhiyun TSI108_IRQ_DIRECTED, 108*4882a593Smuzhiyun TSI108_IRQ_DISTRIBUTED, 109*4882a593Smuzhiyun } TSI108_IRQ_MODE; 110*4882a593Smuzhiyun #endif /* _ASM_POWERPC_TSI108_IRQ_H */ 111