1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2014 IBM Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_PNV_PCI_H 7*4882a593Smuzhiyun #define _ASM_PNV_PCI_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/pci.h> 10*4882a593Smuzhiyun #include <linux/pci_hotplug.h> 11*4882a593Smuzhiyun #include <linux/irq.h> 12*4882a593Smuzhiyun #include <misc/cxl-base.h> 13*4882a593Smuzhiyun #include <asm/opal-api.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PCI_SLOT_ID_PREFIX (1UL << 63) 16*4882a593Smuzhiyun #define PCI_SLOT_ID(phb_id, bdfn) \ 17*4882a593Smuzhiyun (PCI_SLOT_ID_PREFIX | ((uint64_t)(bdfn) << 16) | (phb_id)) 18*4882a593Smuzhiyun #define PCI_PHB_SLOT_ID(phb_id) (phb_id) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun extern int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id); 21*4882a593Smuzhiyun extern int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len); 22*4882a593Smuzhiyun extern int pnv_pci_get_presence_state(uint64_t id, uint8_t *state); 23*4882a593Smuzhiyun extern int pnv_pci_get_power_state(uint64_t id, uint8_t *state); 24*4882a593Smuzhiyun extern int pnv_pci_set_power_state(uint64_t id, uint8_t state, 25*4882a593Smuzhiyun struct opal_msg *msg); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun extern int pnv_pci_set_tunnel_bar(struct pci_dev *dev, uint64_t addr, 28*4882a593Smuzhiyun int enable); 29*4882a593Smuzhiyun int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode); 30*4882a593Smuzhiyun int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 31*4882a593Smuzhiyun unsigned int virq); 32*4882a593Smuzhiyun int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num); 33*4882a593Smuzhiyun void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num); 34*4882a593Smuzhiyun int pnv_cxl_get_irq_count(struct pci_dev *dev); 35*4882a593Smuzhiyun struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev); 36*4882a593Smuzhiyun int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq); 37*4882a593Smuzhiyun bool is_pnv_opal_msi(struct irq_chip *chip); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #ifdef CONFIG_CXL_BASE 40*4882a593Smuzhiyun int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 41*4882a593Smuzhiyun struct pci_dev *dev, int num); 42*4882a593Smuzhiyun void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 43*4882a593Smuzhiyun struct pci_dev *dev); 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct pnv_php_slot { 47*4882a593Smuzhiyun struct hotplug_slot slot; 48*4882a593Smuzhiyun uint64_t id; 49*4882a593Smuzhiyun char *name; 50*4882a593Smuzhiyun int slot_no; 51*4882a593Smuzhiyun unsigned int flags; 52*4882a593Smuzhiyun #define PNV_PHP_FLAG_BROKEN_PDC 0x1 53*4882a593Smuzhiyun struct kref kref; 54*4882a593Smuzhiyun #define PNV_PHP_STATE_INITIALIZED 0 55*4882a593Smuzhiyun #define PNV_PHP_STATE_REGISTERED 1 56*4882a593Smuzhiyun #define PNV_PHP_STATE_POPULATED 2 57*4882a593Smuzhiyun #define PNV_PHP_STATE_OFFLINE 3 58*4882a593Smuzhiyun int state; 59*4882a593Smuzhiyun int irq; 60*4882a593Smuzhiyun struct workqueue_struct *wq; 61*4882a593Smuzhiyun struct device_node *dn; 62*4882a593Smuzhiyun struct pci_dev *pdev; 63*4882a593Smuzhiyun struct pci_bus *bus; 64*4882a593Smuzhiyun bool power_state_check; 65*4882a593Smuzhiyun u8 attention_state; 66*4882a593Smuzhiyun void *fdt; 67*4882a593Smuzhiyun void *dt; 68*4882a593Smuzhiyun struct of_changeset ocs; 69*4882a593Smuzhiyun struct pnv_php_slot *parent; 70*4882a593Smuzhiyun struct list_head children; 71*4882a593Smuzhiyun struct list_head link; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun extern struct pnv_php_slot *pnv_php_find_slot(struct device_node *dn); 74*4882a593Smuzhiyun extern int pnv_php_set_slot_power_state(struct hotplug_slot *slot, 75*4882a593Smuzhiyun uint8_t state); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif 78