1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_POWERPC_PAGE_32_H 3*4882a593Smuzhiyun #define _ASM_POWERPC_PAGE_32_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/cache.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0) 8*4882a593Smuzhiyun #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0 9*4882a593Smuzhiyun #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN" 10*4882a593Smuzhiyun #endif 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifdef CONFIG_NOT_COHERENT_CACHE 16*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef CONFIG_PTE_64BIT 20*4882a593Smuzhiyun #define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */ 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun #define PTE_FLAGS_OFFSET 0 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #if defined(CONFIG_PPC_256K_PAGES) || \ 26*4882a593Smuzhiyun (defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)) 27*4882a593Smuzhiyun #define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */ 28*4882a593Smuzhiyun #else 29*4882a593Smuzhiyun #define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */ 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * The basic type of a PTE - 64 bits for those CPUs with > 32 bit 35*4882a593Smuzhiyun * physical addressing. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #ifdef CONFIG_PTE_64BIT 38*4882a593Smuzhiyun typedef unsigned long long pte_basic_t; 39*4882a593Smuzhiyun #else 40*4882a593Smuzhiyun typedef unsigned long pte_basic_t; 41*4882a593Smuzhiyun #endif 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #include <asm/bug.h> 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Clear page using the dcbz instruction, which doesn't cause any 47*4882a593Smuzhiyun * memory traffic (except to write out any cache lines which get 48*4882a593Smuzhiyun * displaced). This only works on cacheable memory. 49*4882a593Smuzhiyun */ clear_page(void * addr)50*4882a593Smuzhiyunstatic inline void clear_page(void *addr) 51*4882a593Smuzhiyun { 52*4882a593Smuzhiyun unsigned int i; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1)); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES) 57*4882a593Smuzhiyun dcbz(addr); 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun extern void copy_page(void *to, void *from); 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #include <asm-generic/getorder.h> 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) 64*4882a593Smuzhiyun #define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _ASM_POWERPC_PAGE_32_H */ 69