1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on alpha version.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _ASM_POWERPC_OPROFILE_IMPL_H
9*4882a593Smuzhiyun #define _ASM_POWERPC_OPROFILE_IMPL_H
10*4882a593Smuzhiyun #ifdef __KERNEL__
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define OP_MAX_COUNTER 8
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* Per-counter configuration as set via oprofilefs. */
15*4882a593Smuzhiyun struct op_counter_config {
16*4882a593Smuzhiyun unsigned long enabled;
17*4882a593Smuzhiyun unsigned long event;
18*4882a593Smuzhiyun unsigned long count;
19*4882a593Smuzhiyun /* Classic doesn't support per-counter user/kernel selection */
20*4882a593Smuzhiyun unsigned long kernel;
21*4882a593Smuzhiyun unsigned long user;
22*4882a593Smuzhiyun unsigned long unit_mask;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* System-wide configuration as set via oprofilefs. */
26*4882a593Smuzhiyun struct op_system_config {
27*4882a593Smuzhiyun #ifdef CONFIG_PPC64
28*4882a593Smuzhiyun unsigned long mmcr0;
29*4882a593Smuzhiyun unsigned long mmcr1;
30*4882a593Smuzhiyun unsigned long mmcra;
31*4882a593Smuzhiyun #ifdef CONFIG_OPROFILE_CELL
32*4882a593Smuzhiyun /* Register for oprofile user tool to check cell kernel profiling
33*4882a593Smuzhiyun * support.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun unsigned long cell_support;
36*4882a593Smuzhiyun #endif
37*4882a593Smuzhiyun #endif
38*4882a593Smuzhiyun unsigned long enable_kernel;
39*4882a593Smuzhiyun unsigned long enable_user;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Per-arch configuration */
43*4882a593Smuzhiyun struct op_powerpc_model {
44*4882a593Smuzhiyun int (*reg_setup) (struct op_counter_config *,
45*4882a593Smuzhiyun struct op_system_config *,
46*4882a593Smuzhiyun int num_counters);
47*4882a593Smuzhiyun int (*cpu_setup) (struct op_counter_config *);
48*4882a593Smuzhiyun int (*start) (struct op_counter_config *);
49*4882a593Smuzhiyun int (*global_start) (struct op_counter_config *);
50*4882a593Smuzhiyun void (*stop) (void);
51*4882a593Smuzhiyun void (*global_stop) (void);
52*4882a593Smuzhiyun int (*sync_start)(void);
53*4882a593Smuzhiyun int (*sync_stop)(void);
54*4882a593Smuzhiyun void (*handle_interrupt) (struct pt_regs *,
55*4882a593Smuzhiyun struct op_counter_config *);
56*4882a593Smuzhiyun int num_counters;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun extern struct op_powerpc_model op_model_fsl_emb;
60*4882a593Smuzhiyun extern struct op_powerpc_model op_model_power4;
61*4882a593Smuzhiyun extern struct op_powerpc_model op_model_7450;
62*4882a593Smuzhiyun extern struct op_powerpc_model op_model_cell;
63*4882a593Smuzhiyun extern struct op_powerpc_model op_model_pa6t;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* All the classic PPC parts use these */
classic_ctr_read(unsigned int i)67*4882a593Smuzhiyun static inline unsigned int classic_ctr_read(unsigned int i)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun switch(i) {
70*4882a593Smuzhiyun case 0:
71*4882a593Smuzhiyun return mfspr(SPRN_PMC1);
72*4882a593Smuzhiyun case 1:
73*4882a593Smuzhiyun return mfspr(SPRN_PMC2);
74*4882a593Smuzhiyun case 2:
75*4882a593Smuzhiyun return mfspr(SPRN_PMC3);
76*4882a593Smuzhiyun case 3:
77*4882a593Smuzhiyun return mfspr(SPRN_PMC4);
78*4882a593Smuzhiyun case 4:
79*4882a593Smuzhiyun return mfspr(SPRN_PMC5);
80*4882a593Smuzhiyun case 5:
81*4882a593Smuzhiyun return mfspr(SPRN_PMC6);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* No PPC32 chip has more than 6 so far */
84*4882a593Smuzhiyun #ifdef CONFIG_PPC64
85*4882a593Smuzhiyun case 6:
86*4882a593Smuzhiyun return mfspr(SPRN_PMC7);
87*4882a593Smuzhiyun case 7:
88*4882a593Smuzhiyun return mfspr(SPRN_PMC8);
89*4882a593Smuzhiyun #endif
90*4882a593Smuzhiyun default:
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
classic_ctr_write(unsigned int i,unsigned int val)95*4882a593Smuzhiyun static inline void classic_ctr_write(unsigned int i, unsigned int val)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun switch(i) {
98*4882a593Smuzhiyun case 0:
99*4882a593Smuzhiyun mtspr(SPRN_PMC1, val);
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun case 1:
102*4882a593Smuzhiyun mtspr(SPRN_PMC2, val);
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun case 2:
105*4882a593Smuzhiyun mtspr(SPRN_PMC3, val);
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun case 3:
108*4882a593Smuzhiyun mtspr(SPRN_PMC4, val);
109*4882a593Smuzhiyun break;
110*4882a593Smuzhiyun case 4:
111*4882a593Smuzhiyun mtspr(SPRN_PMC5, val);
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun case 5:
114*4882a593Smuzhiyun mtspr(SPRN_PMC6, val);
115*4882a593Smuzhiyun break;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* No PPC32 chip has more than 6, yet */
118*4882a593Smuzhiyun #ifdef CONFIG_PPC64
119*4882a593Smuzhiyun case 6:
120*4882a593Smuzhiyun mtspr(SPRN_PMC7, val);
121*4882a593Smuzhiyun break;
122*4882a593Smuzhiyun case 7:
123*4882a593Smuzhiyun mtspr(SPRN_PMC8, val);
124*4882a593Smuzhiyun break;
125*4882a593Smuzhiyun #endif
126*4882a593Smuzhiyun default:
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #endif /* __KERNEL__ */
135*4882a593Smuzhiyun #endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
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