1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H 3*4882a593Smuzhiyun #define _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H 4*4882a593Smuzhiyun #ifdef __KERNEL__ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based 7*4882a593Smuzhiyun * processors 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun MMU Assist Register 3: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 12*4882a593Smuzhiyun RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - PRESENT *must* be in the bottom three bits because swap cache 15*4882a593Smuzhiyun entries use the top 29 bits. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Definitions for FSL Book-E Cores */ 20*4882a593Smuzhiyun #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */ 21*4882a593Smuzhiyun #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */ 22*4882a593Smuzhiyun #define _PAGE_RW 0x00004 /* S: Write permission (SW) */ 23*4882a593Smuzhiyun #define _PAGE_DIRTY 0x00008 /* S: Page dirty */ 24*4882a593Smuzhiyun #define _PAGE_EXEC 0x00010 /* H: SX permission */ 25*4882a593Smuzhiyun #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define _PAGE_ENDIAN 0x00040 /* H: E bit */ 28*4882a593Smuzhiyun #define _PAGE_GUARDED 0x00080 /* H: G bit */ 29*4882a593Smuzhiyun #define _PAGE_COHERENT 0x00100 /* H: M bit */ 30*4882a593Smuzhiyun #define _PAGE_NO_CACHE 0x00200 /* H: I bit */ 31*4882a593Smuzhiyun #define _PAGE_WRITETHRU 0x00400 /* H: W bit */ 32*4882a593Smuzhiyun #define _PAGE_SPECIAL 0x00800 /* S: Special page */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define _PAGE_KERNEL_RO 0 35*4882a593Smuzhiyun #define _PAGE_KERNEL_ROX _PAGE_EXEC 36*4882a593Smuzhiyun #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) 37*4882a593Smuzhiyun #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* No page size encoding in the linux PTE */ 40*4882a593Smuzhiyun #define _PAGE_PSIZE 0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define _PMD_PRESENT 0 43*4882a593Smuzhiyun #define _PMD_PRESENT_MASK (PAGE_MASK) 44*4882a593Smuzhiyun #define _PMD_BAD (~PAGE_MASK) 45*4882a593Smuzhiyun #define _PMD_USER 0 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define _PTE_NONE_MASK 0 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define PTE_WIMGE_SHIFT (6) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * We define 2 sets of base prot bits, one for basic pages (ie, 53*4882a593Smuzhiyun * cacheable kernel and user pages) and one for non cacheable 54*4882a593Smuzhiyun * pages. We always set _PAGE_COHERENT when SMP is enabled or 55*4882a593Smuzhiyun * the processor might need it for DMA coherency. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 58*4882a593Smuzhiyun #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 59*4882a593Smuzhiyun #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 60*4882a593Smuzhiyun #else 61*4882a593Smuzhiyun #define _PAGE_BASE (_PAGE_BASE_NC) 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Permission masks used to generate the __P and __S table */ 65*4882a593Smuzhiyun #define PAGE_NONE __pgprot(_PAGE_BASE) 66*4882a593Smuzhiyun #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 67*4882a593Smuzhiyun #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 68*4882a593Smuzhiyun #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 69*4882a593Smuzhiyun #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 70*4882a593Smuzhiyun #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 71*4882a593Smuzhiyun #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __KERNEL__ */ 74*4882a593Smuzhiyun #endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */ 75