1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_POWERPC_MMU_40X_H_ 3*4882a593Smuzhiyun #define _ASM_POWERPC_MMU_40X_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * PPC40x support 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define PPC40X_TLB_SIZE 64 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * TLB entries are defined by a "high" tag portion and a "low" data 13*4882a593Smuzhiyun * portion. On all architectures, the data portion is 32-bits. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * TLB entries are managed entirely under software control by reading, 16*4882a593Smuzhiyun * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx 17*4882a593Smuzhiyun * instructions. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define TLB_LO 1 21*4882a593Smuzhiyun #define TLB_HI 0 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define TLB_DATA TLB_LO 24*4882a593Smuzhiyun #define TLB_TAG TLB_HI 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Tag portion */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ 29*4882a593Smuzhiyun #define TLB_PAGESZ_MASK 0x00000380 30*4882a593Smuzhiyun #define TLB_PAGESZ(x) (((x) & 0x7) << 7) 31*4882a593Smuzhiyun #define PAGESZ_1K 0 32*4882a593Smuzhiyun #define PAGESZ_4K 1 33*4882a593Smuzhiyun #define PAGESZ_16K 2 34*4882a593Smuzhiyun #define PAGESZ_64K 3 35*4882a593Smuzhiyun #define PAGESZ_256K 4 36*4882a593Smuzhiyun #define PAGESZ_1M 5 37*4882a593Smuzhiyun #define PAGESZ_4M 6 38*4882a593Smuzhiyun #define PAGESZ_16M 7 39*4882a593Smuzhiyun #define TLB_VALID 0x00000040 /* Entry is valid */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Data portion */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ 44*4882a593Smuzhiyun #define TLB_PERM_MASK 0x00000300 45*4882a593Smuzhiyun #define TLB_EX 0x00000200 /* Instruction execution allowed */ 46*4882a593Smuzhiyun #define TLB_WR 0x00000100 /* Writes permitted */ 47*4882a593Smuzhiyun #define TLB_ZSEL_MASK 0x000000F0 48*4882a593Smuzhiyun #define TLB_ZSEL(x) (((x) & 0xF) << 4) 49*4882a593Smuzhiyun #define TLB_ATTR_MASK 0x0000000F 50*4882a593Smuzhiyun #define TLB_W 0x00000008 /* Caching is write-through */ 51*4882a593Smuzhiyun #define TLB_I 0x00000004 /* Caching is inhibited */ 52*4882a593Smuzhiyun #define TLB_M 0x00000002 /* Memory is coherent */ 53*4882a593Smuzhiyun #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun typedef struct { 58*4882a593Smuzhiyun unsigned int id; 59*4882a593Smuzhiyun unsigned int active; 60*4882a593Smuzhiyun unsigned long vdso_base; 61*4882a593Smuzhiyun } mm_context_t; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define mmu_virtual_psize MMU_PAGE_4K 66*4882a593Smuzhiyun #define mmu_linear_psize MMU_PAGE_256M 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _ASM_POWERPC_MMU_40X_H_ */ 69