1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1997 Geert Uytterhoeven 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is based on the following documentation: 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Macintosh Technology in the Common Hardware Reference Platform 9*4882a593Smuzhiyun * Apple Computer, Inc. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * © Copyright 1995 Apple Computer, Inc. All rights reserved. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * It's available online from https://www.cpu.lu/~mlan/ftp/MacTech.pdf 14*4882a593Smuzhiyun * You can obtain paper copies of this book from computer bookstores or by 15*4882a593Smuzhiyun * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San 16*4882a593Smuzhiyun * Francisco, CA 94104. Reference ISBN 1-55860-393-X. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 19*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 20*4882a593Smuzhiyun * for more details. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef _ASMPPC_HYDRA_H 24*4882a593Smuzhiyun #define _ASMPPC_HYDRA_H 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifdef __KERNEL__ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct Hydra { 29*4882a593Smuzhiyun /* DBDMA Controller Register Space */ 30*4882a593Smuzhiyun char Pad1[0x30]; 31*4882a593Smuzhiyun u_int CachePD; 32*4882a593Smuzhiyun u_int IDs; 33*4882a593Smuzhiyun u_int Feature_Control; 34*4882a593Smuzhiyun char Pad2[0x7fc4]; 35*4882a593Smuzhiyun /* DBDMA Channel Register Space */ 36*4882a593Smuzhiyun char SCSI_DMA[0x100]; 37*4882a593Smuzhiyun char Pad3[0x300]; 38*4882a593Smuzhiyun char SCCA_Tx_DMA[0x100]; 39*4882a593Smuzhiyun char SCCA_Rx_DMA[0x100]; 40*4882a593Smuzhiyun char SCCB_Tx_DMA[0x100]; 41*4882a593Smuzhiyun char SCCB_Rx_DMA[0x100]; 42*4882a593Smuzhiyun char Pad4[0x7800]; 43*4882a593Smuzhiyun /* Device Register Space */ 44*4882a593Smuzhiyun char SCSI[0x1000]; 45*4882a593Smuzhiyun char ADB[0x1000]; 46*4882a593Smuzhiyun char SCC_Legacy[0x1000]; 47*4882a593Smuzhiyun char SCC[0x1000]; 48*4882a593Smuzhiyun char Pad9[0x2000]; 49*4882a593Smuzhiyun char VIA[0x2000]; 50*4882a593Smuzhiyun char Pad10[0x28000]; 51*4882a593Smuzhiyun char OpenPIC[0x40000]; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun extern volatile struct Hydra __iomem *Hydra; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Feature Control Register 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ 62*4882a593Smuzhiyun #define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ 63*4882a593Smuzhiyun #define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ 64*4882a593Smuzhiyun #define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ 65*4882a593Smuzhiyun #define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ 66*4882a593Smuzhiyun #define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ 67*4882a593Smuzhiyun #define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ 68*4882a593Smuzhiyun #define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ 69*4882a593Smuzhiyun #define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * OpenPIC Interrupt Sources 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define HYDRA_INT_SIO 0 77*4882a593Smuzhiyun #define HYDRA_INT_SCSI_DMA 1 78*4882a593Smuzhiyun #define HYDRA_INT_SCCA_TX_DMA 2 79*4882a593Smuzhiyun #define HYDRA_INT_SCCA_RX_DMA 3 80*4882a593Smuzhiyun #define HYDRA_INT_SCCB_TX_DMA 4 81*4882a593Smuzhiyun #define HYDRA_INT_SCCB_RX_DMA 5 82*4882a593Smuzhiyun #define HYDRA_INT_SCSI 6 83*4882a593Smuzhiyun #define HYDRA_INT_SCCA 7 84*4882a593Smuzhiyun #define HYDRA_INT_SCCB 8 85*4882a593Smuzhiyun #define HYDRA_INT_VIA 9 86*4882a593Smuzhiyun #define HYDRA_INT_ADB 10 87*4882a593Smuzhiyun #define HYDRA_INT_ADB_NMI 11 88*4882a593Smuzhiyun #define HYDRA_INT_EXT1 12 /* PCI IRQW */ 89*4882a593Smuzhiyun #define HYDRA_INT_EXT2 13 /* PCI IRQX */ 90*4882a593Smuzhiyun #define HYDRA_INT_EXT3 14 /* PCI IRQY */ 91*4882a593Smuzhiyun #define HYDRA_INT_EXT4 15 /* PCI IRQZ */ 92*4882a593Smuzhiyun #define HYDRA_INT_EXT5 16 /* IDE Primary/Secondary */ 93*4882a593Smuzhiyun #define HYDRA_INT_EXT6 17 /* IDE Secondary */ 94*4882a593Smuzhiyun #define HYDRA_INT_EXT7 18 /* Power Off Request */ 95*4882a593Smuzhiyun #define HYDRA_INT_SPARE 19 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun extern int hydra_init(void); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif /* __KERNEL__ */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif /* _ASMPPC_HYDRA_H */ 102