1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_POWERPC_HEATHROW_H 3*4882a593Smuzhiyun #define _ASM_POWERPC_HEATHROW_H 4*4882a593Smuzhiyun #ifdef __KERNEL__ 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * heathrow.h: definitions for using the "Heathrow" I/O controller chip. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Grabbed from Open Firmware definitions on a PowerBook G3 Series 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright (C) 1997 Paul Mackerras. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Front light color on Yikes/B&W G3. 32 bits */ 14*4882a593Smuzhiyun #define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Brightness/contrast (gossamer iMac ?). 8 bits */ 17*4882a593Smuzhiyun #define HEATHROW_BRIGHTNESS_CNTL 0x32 18*4882a593Smuzhiyun #define HEATHROW_CONTRAST_CNTL 0x33 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* offset from ohare base for feature control register */ 21*4882a593Smuzhiyun #define HEATHROW_MBCR 0x34 /* Media bay control */ 22*4882a593Smuzhiyun #define HEATHROW_FCR 0x38 /* Feature control */ 23*4882a593Smuzhiyun #define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Bits in feature control register. 27*4882a593Smuzhiyun * Bits postfixed with a _N are in inverse logic 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */ 30*4882a593Smuzhiyun #define HRW_BAY_POWER_N 0x00000002 31*4882a593Smuzhiyun #define HRW_BAY_PCI_ENABLE 0x00000004 32*4882a593Smuzhiyun #define HRW_BAY_IDE_ENABLE 0x00000008 33*4882a593Smuzhiyun #define HRW_BAY_FLOPPY_ENABLE 0x00000010 34*4882a593Smuzhiyun #define HRW_IDE0_ENABLE 0x00000020 35*4882a593Smuzhiyun #define HRW_IDE0_RESET_N 0x00000040 36*4882a593Smuzhiyun #define HRW_BAY_DEV_MASK 0x0000001c 37*4882a593Smuzhiyun #define HRW_BAY_RESET_N 0x00000080 38*4882a593Smuzhiyun #define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */ 39*4882a593Smuzhiyun #define HRW_SCC_ENABLE 0x00000200 40*4882a593Smuzhiyun #define HRW_MESH_ENABLE 0x00000400 41*4882a593Smuzhiyun #define HRW_SWIM_ENABLE 0x00000800 42*4882a593Smuzhiyun #define HRW_SOUND_POWER_N 0x00001000 43*4882a593Smuzhiyun #define HRW_SOUND_CLK_ENABLE 0x00002000 44*4882a593Smuzhiyun #define HRW_SCCA_IO 0x00004000 45*4882a593Smuzhiyun #define HRW_SCCB_IO 0x00008000 46*4882a593Smuzhiyun #define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */ 47*4882a593Smuzhiyun #define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */ 48*4882a593Smuzhiyun #define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */ 49*4882a593Smuzhiyun #define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */ 50*4882a593Smuzhiyun #define HRW_AUD_RUN22 0x00100000 /* ??? (1) */ 51*4882a593Smuzhiyun #define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */ 52*4882a593Smuzhiyun #define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */ 53*4882a593Smuzhiyun #define HRW_IDE1_RESET_N 0x00800000 /* Media bay */ 54*4882a593Smuzhiyun #define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */ 55*4882a593Smuzhiyun #define HRW_RESET_SCC 0x02000000 56*4882a593Smuzhiyun #define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */ 57*4882a593Smuzhiyun #define HRW_USE_MFDC 0x08000000 /* ??? (0) */ 58*4882a593Smuzhiyun #define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */ 59*4882a593Smuzhiyun #define HRW_BMAC_RESET 0x80000000 /* not documented in OF */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* We OR those features at boot on desktop G3s */ 62*4882a593Smuzhiyun #define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Looks like Heathrow has some sort of GPIOs as well... */ 65*4882a593Smuzhiyun #define HRW_GPIO_MODEM_RESET 0x6d 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __KERNEL__ */ 68*4882a593Smuzhiyun #endif /* _ASM_POWERPC_HEATHROW_H */ 69