1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __FSL_PAMU_STASH_H 8*4882a593Smuzhiyun #define __FSL_PAMU_STASH_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* cache stash targets */ 11*4882a593Smuzhiyun enum pamu_stash_target { 12*4882a593Smuzhiyun PAMU_ATTR_CACHE_L1 = 1, 13*4882a593Smuzhiyun PAMU_ATTR_CACHE_L2, 14*4882a593Smuzhiyun PAMU_ATTR_CACHE_L3, 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * This attribute allows configuring stashig specific parameters 19*4882a593Smuzhiyun * in the PAMU hardware. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct pamu_stash_attribute { 23*4882a593Smuzhiyun u32 cpu; /* cpu number */ 24*4882a593Smuzhiyun u32 cache; /* cache to stash to: L1,L2,L3 */ 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #endif /* __FSL_PAMU_STASH_H */ 28