1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Definitions for using the Apple Descriptor-Based DMA controller 4*4882a593Smuzhiyun * in Power Macintosh computers. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1996 Paul Mackerras. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifdef __KERNEL__ 10*4882a593Smuzhiyun #ifndef _ASM_DBDMA_H_ 11*4882a593Smuzhiyun #define _ASM_DBDMA_H_ 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * DBDMA control/status registers. All little-endian. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct dbdma_regs { 16*4882a593Smuzhiyun unsigned int control; /* lets you change bits in status */ 17*4882a593Smuzhiyun unsigned int status; /* DMA and device status bits (see below) */ 18*4882a593Smuzhiyun unsigned int cmdptr_hi; /* upper 32 bits of command address */ 19*4882a593Smuzhiyun unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */ 20*4882a593Smuzhiyun unsigned int intr_sel; /* select interrupt condition bit */ 21*4882a593Smuzhiyun unsigned int br_sel; /* select branch condition bit */ 22*4882a593Smuzhiyun unsigned int wait_sel; /* select wait condition bit */ 23*4882a593Smuzhiyun unsigned int xfer_mode; 24*4882a593Smuzhiyun unsigned int data2ptr_hi; 25*4882a593Smuzhiyun unsigned int data2ptr; 26*4882a593Smuzhiyun unsigned int res1; 27*4882a593Smuzhiyun unsigned int address_hi; 28*4882a593Smuzhiyun unsigned int br_addr_hi; 29*4882a593Smuzhiyun unsigned int res2[3]; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Bits in control and status registers */ 33*4882a593Smuzhiyun #define RUN 0x8000 34*4882a593Smuzhiyun #define PAUSE 0x4000 35*4882a593Smuzhiyun #define FLUSH 0x2000 36*4882a593Smuzhiyun #define WAKE 0x1000 37*4882a593Smuzhiyun #define DEAD 0x0800 38*4882a593Smuzhiyun #define ACTIVE 0x0400 39*4882a593Smuzhiyun #define BT 0x0100 40*4882a593Smuzhiyun #define DEVSTAT 0x00ff 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * DBDMA command structure. These fields are all little-endian! 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun struct dbdma_cmd { 46*4882a593Smuzhiyun __le16 req_count; /* requested byte transfer count */ 47*4882a593Smuzhiyun __le16 command; /* command word (has bit-fields) */ 48*4882a593Smuzhiyun __le32 phy_addr; /* physical data address */ 49*4882a593Smuzhiyun __le32 cmd_dep; /* command-dependent field */ 50*4882a593Smuzhiyun __le16 res_count; /* residual count after completion */ 51*4882a593Smuzhiyun __le16 xfer_status; /* transfer status */ 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* DBDMA command values in command field */ 55*4882a593Smuzhiyun #define OUTPUT_MORE 0 /* transfer memory data to stream */ 56*4882a593Smuzhiyun #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ 57*4882a593Smuzhiyun #define INPUT_MORE 0x2000 /* transfer stream data to memory */ 58*4882a593Smuzhiyun #define INPUT_LAST 0x3000 /* ditto, expect end marker */ 59*4882a593Smuzhiyun #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ 60*4882a593Smuzhiyun #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ 61*4882a593Smuzhiyun #define DBDMA_NOP 0x6000 /* do nothing */ 62*4882a593Smuzhiyun #define DBDMA_STOP 0x7000 /* suspend processing */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Key values in command field */ 65*4882a593Smuzhiyun #define KEY_STREAM0 0 /* usual data stream */ 66*4882a593Smuzhiyun #define KEY_STREAM1 0x100 /* control/status stream */ 67*4882a593Smuzhiyun #define KEY_STREAM2 0x200 /* device-dependent stream */ 68*4882a593Smuzhiyun #define KEY_STREAM3 0x300 /* device-dependent stream */ 69*4882a593Smuzhiyun #define KEY_REGS 0x500 /* device register space */ 70*4882a593Smuzhiyun #define KEY_SYSTEM 0x600 /* system memory-mapped space */ 71*4882a593Smuzhiyun #define KEY_DEVICE 0x700 /* device memory-mapped space */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Interrupt control values in command field */ 74*4882a593Smuzhiyun #define INTR_NEVER 0 /* don't interrupt */ 75*4882a593Smuzhiyun #define INTR_IFSET 0x10 /* intr if condition bit is 1 */ 76*4882a593Smuzhiyun #define INTR_IFCLR 0x20 /* intr if condition bit is 0 */ 77*4882a593Smuzhiyun #define INTR_ALWAYS 0x30 /* always interrupt */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Branch control values in command field */ 80*4882a593Smuzhiyun #define BR_NEVER 0 /* don't branch */ 81*4882a593Smuzhiyun #define BR_IFSET 0x4 /* branch if condition bit is 1 */ 82*4882a593Smuzhiyun #define BR_IFCLR 0x8 /* branch if condition bit is 0 */ 83*4882a593Smuzhiyun #define BR_ALWAYS 0xc /* always branch */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Wait control values in command field */ 86*4882a593Smuzhiyun #define WAIT_NEVER 0 /* don't wait */ 87*4882a593Smuzhiyun #define WAIT_IFSET 1 /* wait if condition bit is 1 */ 88*4882a593Smuzhiyun #define WAIT_IFCLR 2 /* wait if condition bit is 0 */ 89*4882a593Smuzhiyun #define WAIT_ALWAYS 3 /* always wait */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Align an address for a DBDMA command structure */ 92*4882a593Smuzhiyun #define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \ 93*4882a593Smuzhiyun & -sizeof(struct dbdma_cmd)) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Useful macros */ 96*4882a593Smuzhiyun #define DBDMA_DO_STOP(regs) do { \ 97*4882a593Smuzhiyun out_le32(&((regs)->control), (RUN|FLUSH)<<16); \ 98*4882a593Smuzhiyun while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \ 99*4882a593Smuzhiyun ; \ 100*4882a593Smuzhiyun } while(0) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define DBDMA_DO_RESET(regs) do { \ 103*4882a593Smuzhiyun out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\ 104*4882a593Smuzhiyun while(in_le32(&((regs)->status)) & (RUN)) \ 105*4882a593Smuzhiyun ; \ 106*4882a593Smuzhiyun } while(0) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* _ASM_DBDMA_H_ */ 109*4882a593Smuzhiyun #endif /* __KERNEL__ */ 110